hello Craig,
It is about 12 years ago. We made a circuit that indeed enabled us to evaluate reclocking on data, wclk and le separately.
The Latch was most sensitive to reclocking, as expected. Data and wclk where slightly sensitive, reclcoking improved playback quality but only about 10% of the improvement made when reclocking LE.
Needless to say that one needs separate reclockers AND power supplies for all 3 signals, as we implemented in all our newest DAC designs.
best
Hi there!
This post has been off for years... but I would like to raise some questions... and thank werewolf for the nice description of the topic!
First I would like to re-state the goal of the ASRC for this application... and see if I understood well all... ;
a) the goal is to use an ASRC to change the sampling rate of a digital signal transmitted to a DAC in some other distant place.
b) The idea behind this sampling rate translation is to adapt (re-sample)the data of the signal to the new clock clocking the DAC. This is, to recover the original spectrum of the signal, by re-sampling the data to the new rate at the local DAC clock (which is supposed to be close to the receiver).
c) The ASRC is called asynchronous because the ratio is incommensurate and it might fluctuate...
d) You still need two clocks, one recovered from the digital signal and the second, the local clock, for the DAC and to which you re-sample the signal
Is this right?
Now going forward...
You showed the process with a polyphase architecture... there you just use the received clock (extracted from the data stream) to compute, together with the local clock, which phase you use. Then you compute the output sample by filtering the input data with the selected phase using hardware clocked with the local clock... is this right?
A bit more forward... what about the farrow architecture?, which is more hardware efficient... was a technology limitation 15 years ago to use such scheme?
If going for a farrow... the re-sampling ratio would fluctuate, having the output clock (local) fix, right? the ASRC would correct the fluctuations of the incoming clock to the output one... right?
Do you know any implementation of such an algorithm/system?
Thanks a lot and sorry for my poor english!
This post has been off for years... but I would like to raise some questions... and thank werewolf for the nice description of the topic!
First I would like to re-state the goal of the ASRC for this application... and see if I understood well all... ;
a) the goal is to use an ASRC to change the sampling rate of a digital signal transmitted to a DAC in some other distant place.
b) The idea behind this sampling rate translation is to adapt (re-sample)the data of the signal to the new clock clocking the DAC. This is, to recover the original spectrum of the signal, by re-sampling the data to the new rate at the local DAC clock (which is supposed to be close to the receiver).
c) The ASRC is called asynchronous because the ratio is incommensurate and it might fluctuate...
d) You still need two clocks, one recovered from the digital signal and the second, the local clock, for the DAC and to which you re-sample the signal
Is this right?
Now going forward...
You showed the process with a polyphase architecture... there you just use the received clock (extracted from the data stream) to compute, together with the local clock, which phase you use. Then you compute the output sample by filtering the input data with the selected phase using hardware clocked with the local clock... is this right?
A bit more forward... what about the farrow architecture?, which is more hardware efficient... was a technology limitation 15 years ago to use such scheme?
If going for a farrow... the re-sampling ratio would fluctuate, having the output clock (local) fix, right? the ASRC would correct the fluctuations of the incoming clock to the output one... right?
Do you know any implementation of such an algorithm/system?
Thanks a lot and sorry for my poor english!
Very interesting discussion on an asrc from Werewolf and others. I am wondering what the trade-off is between using a HUGE polyphase structure vs a sinx/x filter applied to the input samples. The filter's delay coefficients would be re-calculated on the fly according to the frequency relation between input and output clocks. The calculation could be done in DSP software. The delta clock frequencies could be obtained by examining the relative levels of input and output FIFO's containing the samples. This could, at the same time, greatly improve jitter tolerance.
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