While searching in my drawers for the 74CH125 specified in Elso's schematic I found out that I have none.
Since it seems to me a ordinary buffer/line driver I started looking for equivalents.
I have a lot of boards to salvage that mount the 244 octal buffer in various flavours (HC, HCT, F, AC...), as well as some 74F125 which is twice as fast as the HC.
Can I use this or the "F" series carries some issues that make it unsuitable?
Among these logic families, which ones can work best?
Attached is the schematic I'm referring to (posted by Elso Kwak)
Cheers
Andrea.
Edit: the 5V can be taken from the player(maybe with some LC filtering or I'd better use a separate PS?)
Since it seems to me a ordinary buffer/line driver I started looking for equivalents.
I have a lot of boards to salvage that mount the 244 octal buffer in various flavours (HC, HCT, F, AC...), as well as some 74F125 which is twice as fast as the HC.
Can I use this or the "F" series carries some issues that make it unsuitable?
Among these logic families, which ones can work best?
Attached is the schematic I'm referring to (posted by Elso Kwak)
Cheers
Andrea.
Edit: the 5V can be taken from the player(maybe with some LC filtering or I'd better use a separate PS?)
Attachments
Guido Tent said:
Hello Guido,
I think Elso added the buffers to drive a coax cable for each data line, since the DAC itself is placed outside the CD player housing for RFI reasons(I suppose).
Initially I was thinking to omit this circuit and place my DAC inside the player (adding a supply for it), but I experienced serious RFI problems only placing my external TDA1543 DAC on the top of the player (Philips CD931) so now I'm quite doubtful about it.
For the clock, what do you mean? I think I'll replace the player's one but AFAIK no other clocks are needed using IIS direct..
can you elaborate a little?Cheers
Andrea
Edit: partial answer to my question.. using a TTL buffer followed by a emitter follower greatly degrades the noise margin of the circuit, so I think I must use a HC one.
Andypairo said:
Hello Guido,
I think Elso added the buffers to drive a coax cable for each data line, since the DAC itself is placed outside the CD player housing for RFI reasons(I suppose).
Initially I was thinking to omit this circuit and place my DAC inside the player (adding a supply for it), but I experienced serious RFI problems only placing my external TDA1543 DAC on the top of the player (Philips CD931) so now I'm quite doubtful about it.
For the clock, what do you mean? I think I'll replace the player's one but AFAIK no other clocks are needed using IIS direct..
Cheers
Andrea
Edit: partial answer to my question.. using a TTL buffer followed by a emitter follower greatly degrades the noise margin of the circuit, so I think I must use a HC one.
Andrea
If you use the buffer, then why the E-follower ?
Clock should be as close as possible to the DAC, where the party is ! Feed it back to help generating I2S
RFI: Weird, shouldn't be a problem to combine a drive and a DAC chip.....
Ciao
Guido Tent said:
I think the e-follower is to drive the 50 Ohm-terminated cable (surely Elso can explain us his choice much better than me), if the DAC is kept internal maybe the buffer is also unnecessary (unless you parallel too many chips)..
So the clock should feed the DAC (like in DDDAC ?) and then be brought back to the transport?
About RFI I remember that the SPDIF output of my player wans't considered that well... maybe it's just a problem of that interface...
Cheers
Andrea
I2S Direct
Hi Andrea and Guido,
What, do I have to explain this very simple circuit to an EE?
Please read for CDP: CD player component and DAC is DAC component. These are two cases connected with 60 cm 50 Ohm coax cables.
As Andrea indicated the Masterclock is not needed or used in the NON-OS DAC. So why bring it back? I explained this earlier to Lars Clausen. Is the NON-OS concept so difficult to digest? In your words "there is no party for the Masterclock at the NON-OS DAC".
Then the circuit is taken directly from Horowitz page 612 fig. 9.42 in my second edition. Here is also explained why direct logic drive of long coax cables is not feasible.
Now for the buffer: why it is there? No, I don't have to explain that....[hint: figure what happens if you short the transistor...] Oh no, leave the buffer away but don't email me helping solving the problem...
Andrea I only had at hand 74HC125 in DIL and did not want to fiddle with MC74VHC125 in SMD. Maybe VHC logic works better here, but I have not yet tested that. AC logic should be avoided as the black pest and F logic is obsolete. HCT or VHCT will probably also work.
Ciao 
Hi Andrea and Guido,
What, do I have to explain this very simple circuit to an EE?
Please read for CDP: CD player component and DAC is DAC component. These are two cases connected with 60 cm 50 Ohm coax cables.As Andrea indicated the Masterclock is not needed or used in the NON-OS DAC. So why bring it back? I explained this earlier to Lars Clausen. Is the NON-OS concept so difficult to digest? In your words "there is no party for the Masterclock at the NON-OS DAC".
Then the circuit is taken directly from Horowitz page 612 fig. 9.42 in my second edition. Here is also explained why direct logic drive of long coax cables is not feasible.
Now for the buffer: why it is there? No, I don't have to explain that....[hint: figure what happens if you short the transistor...] Oh no, leave the buffer away but don't email me helping solving the problem...
Andrea I only had at hand 74HC125 in DIL and did not want to fiddle with MC74VHC125 in SMD. Maybe VHC logic works better here, but I have not yet tested that. AC logic should be avoided as the black pest and F logic is obsolete. HCT or VHCT will probably also work.
Ciao
dear all,
EVERY DAC needs a clock to convert the data to something analog, regardless of the level of oversampling. Is DA conversion so difficult to digest ? Needless to say that a 1541 has a clock input.
If you use asynchronuous clocking, you can have a free running clock close to the DAC (but I am still not convinced of this principle)
Buffers: The example is too complex. I suggest an E follower, current source loaded with a 47 ohm series resistor to the output, to make it a characteristic driver impedance
Elso, others, I'd suggest to use true transmission line with proper driving / terminating. The jitter (for example due to non characteristic system) in the I2S signals definitely ripples through the DAC, wasting the sound (regardless of the clock used there).
regards
EVERY DAC needs a clock to convert the data to something analog, regardless of the level of oversampling. Is DA conversion so difficult to digest ? Needless to say that a 1541 has a clock input.
If you use asynchronuous clocking, you can have a free running clock close to the DAC (but I am still not convinced of this principle)
Buffers: The example is too complex. I suggest an E follower, current source loaded with a 47 ohm series resistor to the output, to make it a characteristic driver impedance
Elso, others, I'd suggest to use true transmission line with proper driving / terminating. The jitter (for example due to non characteristic system) in the I2S signals definitely ripples through the DAC, wasting the sound (regardless of the clock used there).
regards
I2S Direct
Sorry Guido you still don't understand it.
In fact the TDA1543 is used. The Master clock is not equal to the bit clock. I do not want to generate a Master clock at the DAC divide it down to make it a bit clock and send the Master clock back to the transport.
Asynchronous Reclocking is NOT used in this example.
If you want to improve my circuit be my guest. But Andreas question was what buffer to use in place of 47HC125.
Again the circuit was taken from Horowitz and works better than a SPDIF with CS8412. The cable is properly terminated at the receiving end to avoid reflections. If you want it to terminate at the transmitters end too, see what happens when using an emitter follower.
As for you following post all three signals are in one chip at the SAA7310 & the TDA1543. And Tiny Logic, he I have seen that before. Wasn't it at the Lcaudio clock XO-2?
Besides all this, you did not seriously consider my arguments....
Guido Tent said:
Sorry Guido you still don't understand it.
In fact the TDA1543 is used. The Master clock is not equal to the bit clock. I do not want to generate a Master clock at the DAC divide it down to make it a bit clock and send the Master clock back to the transport.
Asynchronous Reclocking is NOT used in this example.
If you want to improve my circuit be my guest. But Andreas question was what buffer to use in place of 47HC125.
Again the circuit was taken from Horowitz and works better than a SPDIF with CS8412. The cable is properly terminated at the receiving end to avoid reflections. If you want it to terminate at the transmitters end too, see what happens when using an emitter follower.
As for you following post all three signals are in one chip at the SAA7310 & the TDA1543. And Tiny Logic, he I have seen that before. Wasn't it at the Lcaudio clock XO-2?
Besides all this, you did not seriously consider my arguments....
Re: I2S Direct
Elso,
I think the discussion is about definitions (of clocks, bitclock, masterclock, whatever). And yes, I2S is way better than SPDIF, no argument about that. Again, I understand that async clocking does not need feedback, but otherwise it is still advised to generate (and even divide) the clock at the DAC and feed it back.....
What arguments did I miss ?
regards
Elso Kwak said:
Sorry Guido you still don't understand it.
In fact the TDA1543 is used. The Master clock is not equal to the bit clock. I do not want to generate a Master clock at the DAC divide it down to make it a bit clock and send the Master clock back to the transport.
Asynchronous Reclocking is NOT used in this example.
If you want to improve my circuit be my guest. But Andreas question was what buffer to use in place of 47HC125.
Again the circuit was taken from Horowitz and works better than a SPDIF with CS8412. The cable is properly terminated at the receiving end to avoid reflections. If you want it to terminate at the transmitters end too, see what happens when using an emitter follower.
As for you following post all three signals are in one chip at the SAA7310 & the TDA1543. And Tiny Logic, he I have seen that before. Wasn't it at the Lcaudio clock XO-2?
Besides all this, you did not seriously consider my arguments....
Elso,
I think the discussion is about definitions (of clocks, bitclock, masterclock, whatever). And yes, I2S is way better than SPDIF, no argument about that. Again, I understand that async clocking does not need feedback, but otherwise it is still advised to generate (and even divide) the clock at the DAC and feed it back.....
What arguments did I miss ?
regards
Well, I stay away for a couple of hours and things get hot!
The difference between IIS clock and master clock made me difficult to understand how to send the clock back to the transport, thank you Elso for pointing the question out, now is more clear.
To be true the EE is on vacation! 
More seriously, I can analyze a circuit but I can't always tell from it what was the designer's purpose.
And yes, it is still on page 612 ( I have 2nd version too) but Horowitz uses a 10 Ohm from 5V to the collector of the BJT for circuit protection... don't know if I can leave the buffer out, have to take a look at the drive capability of the SAA7310, especially if I want to use some stacked TDA1543s.....
Cheers
Andrea
The difference between IIS clock and master clock made me difficult to understand how to send the clock back to the transport, thank you Elso for pointing the question out, now is more clear.
To be true the EE is on vacation!
More seriously, I can analyze a circuit but I can't always tell from it what was the designer's purpose.
And yes, it is still on page 612 ( I have 2nd version too) but Horowitz uses a 10 Ohm from 5V to the collector of the BJT for circuit protection... don't know if I can leave the buffer out, have to take a look at the drive capability of the SAA7310, especially if I want to use some stacked TDA1543s.....
Cheers
Andrea
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