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Old 16th April 2011, 12:26 PM   #281
RayCtech is offline RayCtech
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Quote:
Originally Posted by Bunpei View Post
Dear RayCTech,

Your discussion in theory is completely correct. I2S has a fatal defect.
My technical background is in a computer science. No data transmission without error corrections can be acceptable in the field in principle.

Therefore, we must do our best for eliminating transmission errors in I2S. In my system where SDTrans192 Rev. 2.1 that you kindly upgraded power supplies for us is connected to TPA Buffalo II via I2S. The wires are shielded and wire length does not exceed an inch.

I can prove that absolutely no errors that you worry happen in my system.
If any erroneous bit flip occurs so frequently, you will always detect a large spike noise. You might easily think the system would be defective. I have never heard such spike noises.

Lets say that we will send 10,000 samples:
1. A zero sample at -96.3dB. 0b0000000000000000
2. A zero sample at -96.3dB. 0b0000000000000000
....
10000. A zero sample at -96.3dB. 0b0000000000000000
When
50. A zero sample at -96.3dB. 0b0000000000000000
is mis-received as
50. A negative sample at 0.0dB. 0b1000000000000000

If the erroneous bit flip occurs so frequently, every datasheet of receiver chip would excuse, "We handle data errors in this way, ....". Have your ever read such descriptions?

If you want to argue your point, please show us your clear actual recorded and reproducible evidences that bit flip errors happen during I2S connection.

Bunpei
you rules by confusion
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Old 17th April 2011, 12:38 AM   #282
Bunpei is offline Bunpei  Japan
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Default I2S specification

Before I explain Chiaki's approach on
"2. handling of BCLK signal"
I want to talk about I2S bus a little bit.

According to Wikipedia,
IS - Wikipedia, the free encyclopedia
"I2S, also known as Inter-IC Sound, Integrated Interchip Sound, or IIS, is an electrical serial bus interface standard used for connecting digital audio devices together."

In the case of S/PDIF, it is standardized in IEC 60958 as IEC 60958 type II (IEC 958 before 1998[2]).
As for I2S, though it is a de facto industry standard, it is not a standard that was standardized by an international standardizing organization. You can read its specification originally published by Philips.
http://www.nxp.com/acrobat_download/various/I2SBUS.pdf
This is the last revision dated June 5, 1996.
I'd like to recommend that you read the spec when you talk about I2S in an engineering context.

In my several experiences of using I2S, I have encountered some incompatibilities on
A. Master clock
B. Bit Clock(SCK) rate
C. Voltage level
As I2S is not a solid, well-defined specification like S/PDIF, you need to pay attentions to the points above proactively so that you may avoid possible problems on I2S. First of all, names of signals vary depending on each manufacturer.

A. Master clock
Strictly speaking, a master clock signal is not included in I2S. However, some DAC chips require a master clock that is an integer multiple of sampling frequency, fs, namely, Word Clock frequency. A master clock is used not for sample timing control but for a fundamental system clock for such internal circuits as DSP function for oversampling filtering.
A frequency requirement for master clock is usually fs dependent. The more you apply high resolution audio sources, the more you need a high frequency master clock. Even if your DAC chip could play sounds with lower frequency master clock than required, the under-run malfunction would happen in OSF.
In the case of ESS ES9018, its master clock frequency and timing can be independent from fs because the DAC adopts an asynchronous data processing scheme. For this chip, the accuracy of master clock is very important when we want to get a high quality sonic result.

B. Bit Clock(SCK) rate
Frequency requirements I have ever seen for Bit Clock is either 32*fs or 64*fs. The former is only applicable to 16bit LPCM data and the latter is to 16, 24, 32bit. I have never seen 48*fs specific to 24bt.
Our first MicroSD memory card player that Chiaki made with VS1053b chip outputs only 32*fs. SDTrans192, 64*fs only. ESS ES9018 DAC chip accepts 64*fs only. Wolfson WM8741 accepts both 32*fs and 64*fs.
Therefore, ES9018 can't be connected to VS1053b output while WM8741 can be connected to VS1053b and SDTrans192. You can't connect SDTrans192 to 32*fs-accepting-only DAC chip.

C. Voltage level
Strictly speaking, the original I2S specification only refers a TTL logic level. Nowadays, most of DAC chips available are compatible to a CMOS logic level.
SDTrans192's I2S direct output is CMOS logic level compatible.
SDTrans192 Rev. 3.0 has PS-Audio type I2S interface, "I2S on LVDS/HDMI connector and cable". On this interface, its voltage level is LVDS, differential.This new interface is compatible to Fidelix CAPRICE DAC and PS-Audio PerfectWave DAC.
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Old 17th April 2011, 05:33 PM   #283
Bunpei is offline Bunpei  Japan
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Default 352.8 kHz/24 bit play on AK4399 DAC

In "Digital Line > exaU2I - Multi-Channel Asynchronous USB to I2S Interface" thread, SanRa first reported that he could play 352.8 kHz audio files on AK4396 192kHz/24bit DAC connected to exaDevices exaU2I interface via I2S.

I tried playing 2L DXD audio files on AK4399 192kHz/32 bit DAC (built in AKD4399-SB evaluation board) using my SDTrans192 Rev. 2.1 and could confirm quite similar results reported by SanRa.
He described the noise that he listened as "hiss" while I'd like to call it "continuous noise". The noise gave me similar impression that I got when I played DXD files with ES9018 of 80MHz master clock.

I believe 2L DXD audio files are "genuine" DXD sources.

I agree with RayCTech's interpretation presented on the exaU2I thread.
As the master clock frequency 22.5792 MHz is a half of the value extrapolated from datasheet value for 176.4kHz, I am afraid that the 8 x oversampling filter in the DAC chip is under-running for 2L DXD LPCM data. This may cause the noise. When I played synthesized sine waves, I had no noises.
The trial of using 45.1584MHz master clock seems interesting.

Anyway, I understand that a sort of "genuine/faked DXD source checker" was discovered by SanRa and RayCTech.
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Old 24th April 2011, 02:49 PM   #284
Bunpei is offline Bunpei  Japan
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Default Importance of Bit Clock signal of I2S

Among three signals in I2S, Bit Clock Signals has the highest frequency. In the case of 352.8 kHz/24 bit, its frequency, 22.5792 MHz, is the same with that of crystal oscillator source. On such a HF range, it's not easy to maintain a good square shape along with its signal path.
Chiaki prepared two paths in FPGA, one is of the least involvement in gate logic circuits in FPGA and another is not the least. We agreed that the former brought a better result.

When we connect I2S signals to ESS ES9018 DAC chip, the quality of Bit Clock is very important because the chip uses Bit Clock for its DPLL functionality. In other words, DPLL bandwidth parameter setting for the DAC chip can be a quantitative measure of quality of the Bit Clock.

A Japanese SDTrans192 Rev. 3.0 user, sunacchi, upgraded power supplies for his SDTrans and achieved a practical setting with "the lowest" bandwidth even on the play of 2L DXD 352.8 kHz/24 bit sources.
Click the image to open in full size.

His Buffalo IIs are configured in Dual Mono mode and controlled with Arduino.
Click the image to open in full size.
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Old 24th April 2011, 05:40 PM   #285
EUVL is offline EUVL  Europe
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352.8kHz x 24bit x 2 channel = 16.934MHz ?

Patrick
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Old 24th April 2011, 06:22 PM   #286
Vil is offline Vil
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Quote:
Originally Posted by EUVL View Post
352.8kHz x 24bit x 2 channel = 16.934MHz ?

Patrick
NO . I2S audio frame is always 64bit (32x2) , so 352.8kHz x 24bit x 2 channel = 22.5792Mhz
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Old 25th April 2011, 02:44 PM   #287
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Vil View Post
NO . I2S audio frame is always 64bit (32x2) , so 352.8kHz x 24bit x 2 channel = 22.5792Mhz
Dear Patrick and Vil,

I hope both of you would read the "B. Bit Clock(SCK) rate" section of my previous explanation on "I2S specification".

Best regards,
Bunpei
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Old 25th April 2011, 02:47 PM   #288
Vil is offline Vil
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Why ? Isn't BCK frequency is 22.5792Mhz for 352.8kHz ?
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Old 25th April 2011, 03:04 PM   #289
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Vil View Post
Why ? Isn't BCK frequency is 22.5792Mhz for 352.8kHz ?
In the case of specific I2S output of SDTrans192, it is true. When we think of various cases in general, for example, for the case where data bit length is 16bit, it would not be true.
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Old 25th April 2011, 03:13 PM   #290
Vil is offline Vil
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I can't agree here . On any pdf of standart manufactured audio IC I never saw I2S with 2x16bit frame . 2x32bit is just standart by default . Maybe with 352.8kHz that becomes overlooked , if yes please confirm that .
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