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Building the ultimate NOS DAC using TDA1541A
Building the ultimate NOS DAC using TDA1541A
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Old 15th October 2018, 11:39 PM   #6701
ryanj is offline ryanj  Australia
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Building the ultimate NOS DAC using TDA1541A
Quote:
Originally Posted by wlowes View Post
I see in the data sheets that VCC can be 2v to 6v and output voltage and current vary based on VCC. So this suggests the 2.5v is within spec and will result in a lower signal on output. So it sounds like I'll get the attenuated signal as a bonus.

I also note however, that switching characteristics of the SN74HC08 depend on VCC. The transition time and propagation delay are reduced at higher VCC. I wonder if running at lower VCC can introduce timing jitter?
The slower rise time may be beneficial, lower bandwidth signal entering dac may cause less interference.
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Old 16th October 2018, 12:39 AM   #6702
wlowes is offline wlowes  Canada
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Excellent. We'll find out in a few days.
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Old 16th October 2018, 07:35 AM   #6703
Zoran is offline Zoran  Serbia
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Quote:
Originally Posted by koldby View Post
Turns out you were right. The LE comes one CLK too early. As I see it the result is , that the 16th bit is thrown away and the hole thing is turned into a 15 bit DAC as it is the LSB that is missing, not the MSB. That does not, IMHO , explain the noise and crackling sounds at high peaks. There must be something else wrong.

Anyway this could be solved by a FF that delays the LE one CLK.
It would be far better, though, to delay it 17 CLK pulses, as this gives TDA1541A time to settle after data has been clocked in, as John has shown.
I said this many posts nefrore but it was ignored...
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Old 16th October 2018, 07:48 AM   #6704
Zoran is offline Zoran  Serbia
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I build 1bit discrete diferential DAC around the idea of tristate logic and ENable input Data. While inputs are tied to + and - power. And it works. The sound is great. For the try I use 4 x HC540. The idea was to make equal impedance outputs from the chip output drivers... Now I am thinking to ehtend to 24 bits but with SIMoultaneous mode stream.
I will try first with 14bit and 16bit version because i already have CPLD interface for that.
I think that MSB has to be NOT inverted, because it is already done by the CPLD?
IF it is not the case 1540 and 1541A wil not work properly, but booth are working very very good with this interface?
Thnks
Cheers
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Old 16th October 2018, 07:59 AM   #6705
batteryman is offline batteryman  United Kingdom
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Quote:
Originally Posted by koldby View Post
Inverting the MSB dosen't work as can be seen from this 4 bit example,
1110 = -2 Invert msb 0110 = 6
1111 = -1 0111 = 7
0000 = 0 1000 = -8
0001 = 1 1001 = -7
0010 = 2 1010 = -6
I thought the dac needed Offset binary for simultaneous mode?
In this case, I naively thought that as the MSB is the sign (polarity) bit, inverting only this would work. EG

0001 = 1
1001 = -1 through to
0111 = 7
1111 = -7

But it only works for some values. Texas' Binary Coding Schemes Technical Note shows that inversion of all bits is needed. (the 1LSB offset could be adjusted at the I/V stage by injecting the LSB current as has been mentioned earlier in this thread)
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Old Yesterday, 05:29 PM   #6706
koldby is offline koldby  Denmark
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Quote:
Originally Posted by batteryman View Post
I thought the dac needed Offset binary for simultaneous mode?
In this case, I naively thought that as the MSB is the sign (polarity) bit, inverting only this would work. EG

0001 = 1
1001 = -1 through to
0111 = 7
1111 = -7

But it only works for some values. Texas' Binary Coding Schemes Technical Note shows that inversion of all bits is needed. (the 1LSB offset could be adjusted at the I/V stage by injecting the LSB current as has been mentioned earlier in this thread)
You are right, I overlooked that fact. But inverting the MSB aparently just changes 2'complement to offset binary and visa versa.
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Old Today, 08:04 AM   #6707
ecdesigns is offline ecdesigns  Netherlands
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Hi ryanj,

Quote:
You dont need to attenuate, but you could if you want to . You could also use a lower voltage reg like the LP5907MFX-2.5/NOPB instead of the LP5907MFX-3.3/NOPB. I think John suggested this a while back, but im yet to give it a go.

It is best to minimise interface signal voltage swing as this lowers the noise being injected in the TDA1541A substrate. Supply voltage as low as 2V4 works reliably, but I would not go much lower than that.

The decoder uses so little power that it can easily be powered by the I2S input signals. I had this issue during testing and I ended up using a 2V4 shunt voltage regulator. So when I2S signal levels are higher than the series voltage regulator voltage, the series voltage regulator becomes ineffective (it's output is simply lifted).

LDO low noise series regulators like the LP5907-2.5 cannot pull down the supply voltage when it's too high, a shunt regulator can.

Other possibility is using the low noise series regulator and attenuate the I2S input signal amplitude to say 2Vpp. This however could introduce problems (increased jitter) with sample timing signal LE.

In order to minimise power supply related propagation delay (and related jitter) it is best to use fast low voltage logic for sample timing (LE in this case). I already took care of this by using a 74LVC1G04 inverter. So supply voltage can be lowered to 2V4 without risking higher jitter level on LE.

The other signals (DOR, DOL, and BCKO) are not critical for jitter as these are not used for sample timing.

Last edited by ecdesigns; Today at 08:06 AM.
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