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Building the ultimate NOS DAC using TDA1541A
Building the ultimate NOS DAC using TDA1541A
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Old 9th June 2018, 04:17 PM   #6191
maxlorenz is online now maxlorenz  Chile
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Quote:
Originally Posted by SSerg View Post
Hi maxlorenz,

I did not say that the Op-Am gives a better sound. Our dispute about the other: the frequency of the DEM generator affects the linearity of the TDA1541 or not. In my opinion, there is influence. And to make sure of this, it is necessary to study the spectra for different DEM frequencies: for the nominal frequency 200 kHz, and 50 Hz, and 500-800 kHz. For this, the I / U cascade on the op-amp is quite suitable.
Yes, I understood this. You are way more knowledgeable than I am, I know this. I was not clear in my post that it was not addressed to you: I only wanted to point out this to the rest of the mates that still use convenience solutions instead of discrete and modifiable subcircuits to experiment better ways of musical reproduction.
My present experiments with low TMD circuits opened my eyes again...

Cheers,
M.
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Old 9th June 2018, 04:23 PM   #6192
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by maxlorenz View Post
I was not clear in my post that it was not addressed to you.
OK
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Old 12th June 2018, 06:06 PM   #6193
xaled is offline xaled
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Quote:
Originally Posted by ecdesigns View Post
Hi xaled,

For a first PCB it looks very good. It is good to see that some DIY audio members take the initiative and design and build something.

Don't forget the ground plane.
Thank you for the compliment. It is nice to know that even the initial draft is not so bad .

I updated the board as far as I could according to your comments. Ground plane was there already, but it did not show up for some reason in the first picture.

I2S-TDA-Boardv1.png

I would appreciate any further comments that would help improve the board.
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Old 12th June 2018, 06:52 PM   #6194
xaled is offline xaled
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Here is another version.
Which one is better?
I2S-TDA-Boardv2.png
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Old 12th June 2018, 09:21 PM   #6195
maxlorenz is online now maxlorenz  Chile
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Quote:
Originally Posted by xaled View Post
Here is another version.
Which one is better?
Attachment 686402
Would Guido Tent's recommendations on the subject of PS chip decoupling be useful in this case?

Best wishes,
M.
Attached Files
File Type: pdf Tentlabs Supply_decoupling.pdf (27.8 KB, 44 views)
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Old 12th June 2018, 11:29 PM   #6196
Zoran is offline Zoran  Serbia
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Can we use some 1x32bit shift register for instance HEF4557B against 4 x 8bit hc164 if the speed and max F are OK?
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Old 20th June 2018, 10:53 AM   #6197
ecdesigns is offline ecdesigns  Netherlands
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Default 4000 series shift registers

Hi zoran,

Quote:
Can we use some 1x32bit shift register for instance HEF4557B against 4 x 8bit hc164 if the speed and max F are OK?
No it's way too slow (propagation delay) to ensure correct operation even at 44.1 KHz while using 5V supply voltage.

The decoder needs to run on 2V4 ... 3V3 supply voltage for low noise.

If you don't like 4 shift registers and only need 16 bit resolution (17 bit with segmented TDA1541A application), it is possible to use clock stopping on the delay shift register.

This way the number of shift registers can be halved while still offering required 32 bit delay (16 bit real data bit delay plus 16 bit paused delay).

We stop the shift register when the bits we don't use / need pass by. These bits do not get clocked in (skipped) when the clock stops, so only the 16 bits we are interested in are temporarily stored in the register.

The delay can be configured for 17 or 24 bit resolution. For 24 bit resolution we need 3 shift registers, for 17 bits only 2 (16 bit data delay and MSB pre-fetch outside the shift register delay circuit).

So we have MSB + 16 bits (2 x 74LV164 delay) = 17 bits.

Or MSB + 24 bits (3 x 74LV164 delay) = 25 bits.

We can use the Q4 counter output (74HC4060) for creating required 16 bit clock burst signal for the shift registers. Invert Q4 (74LVC04) and combine the inverted Q4 output with BCK using an AND gate (74LVC08).

If we need a 24 bit clock burst signal we also have to include the Q3 signal for the decoder.

NOR gate (74LVC02) with Q4 and Q3 outputs connected to its inputs. And gate combines NOR gate output with BCK.
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Old 20th June 2018, 11:32 AM   #6198
ecdesigns is offline ecdesigns  Netherlands
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Hi maxlorenz,

Quote:
Would Guido Tent's recommendations on the subject of PS chip decoupling be useful in this case?
This decoder circuit only needs to handle data. So all we are interested in here is data integrity and that can even be guaranteed with a single decoupling cap (I tested the air wire setup this way).

I use low supply voltage (2V4 ... 3V3) and 1K resistors on the data and bit clock outputs so noise injection (related to fast rising and falling transients) stays low.

The critical signal for timing (if that matters) bypasses the whole circuit and goes straight to the LE sample timing input (TDA1541A in simultaneous mode).

For the USB receiver, decoupling is extremely important, think of noise on the analogue PLL supply.


Decoupling caps also provide more energy for producing more interference. Compare this with short circuiting a 10,000uf cap charged to 63V vs no cap. The higher the peak currents (local charged decoupling cap), the higher the interference. So one has to find a compromise between local supply rail quality (for reliable logic levels) and interference power. It may even be desired to add low Ohmic series resistors to each decoupling cap. This limits local peak switching currents and lowers the Q factor of LC resonance circuits that will always be formed.

Decoupling LC series resonant circuits could make matters worse depending on tuning frequency and target frequency that needs to be attenuated. If such LC resonance is unwanted we need to get LC circuit Q factor down using series or shunt resistors (shunt regulator) for example.

Every single capacitor is basically a LC series resonance circuit that will resonate at a specific frequency. Suppliers often include graphs that show a V curve where impedance drops to the resonance frequency, then rises again (less effective decoupling at these higher frequencies).

When we want to effectively suppress one specific frequency (say 2.8224 MHz bit clock noise) we could create a tuned LC circuit using PCB trace plus decoupling cap inductance plus pure capacitance to resonate at exactly 2.8224 MHz. This would be more effective that simply adding 100nF caps to the board.

Suppose we have total trace inductance (decoupling loop) of say 12nH:

Calculator for the Inductance of a Flat Wire

And we need to tune the decoupling circuit on 2.8224 MHz then we can use this LC calculator:

Resonant Frequency Calculator

We get a pure capacitance of 265nF.

So we could get more effective decoupling by using say 270nF decoupling cap here.

the "standard" 100nF would resonate at 4.59 Mhz and would not be very effective here.

We can also deliberately introduce multiple resonance dips (using different decoupling cap values in combination with trace length) that cover a large bandwidth. This way we can have much more effective decoupling over a much larger bandwidth then simply adding 100nF caps in parallel with each chip.

In the decoder circuit we can have dominant frequencies at 2.8224 MHz, 3.072 MHz, 5.6448 MHz, and 6.144 MHz that we could tackle with tuned decoupling circuits.
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Old 20th June 2018, 02:50 PM   #6199
maxlorenz is online now maxlorenz  Chile
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Quote:
Originally Posted by ecdesigns View Post
Hi maxlorenz,

This decoder circuit only needs to handle data. So all we are interested in here is data integrity and that can even be guaranteed with a single decoupling cap (I tested the air wire setup this way).

For the USB receiver, decoupling is extremely important, think of noise on the analogue PLL supply.

Decoupling LC series resonant circuits could make matters worse depending on tuning frequency and target frequency that needs to be attenuated. If such LC resonance is unwanted we need to get LC circuit Q factor down using series or shunt resistors (shunt regulator) for example.

Every single capacitor is basically a LC series resonance circuit that will resonate at a specific frequency. Suppliers often include graphs that show a V curve where impedance drops to the resonance frequency, then rises again (less effective decoupling at these higher frequencies).

We can also deliberately introduce multiple resonance dips (using different decoupling cap values in combination with trace length) that cover a large bandwidth. This way we can have much more effective decoupling over a much larger bandwidth then simply adding 100nF caps in parallel with each chip.

In the decoder circuit we can have dominant frequencies at 2.8224 MHz, 3.072 MHz, 5.6448 MHz, and 6.144 MHz that we could tackle with tuned decoupling circuits.
Thanks -EC- for that very interesting input.

Reality is like an onion: when you are perfectly happy with the outer coat, you realize that there is always one other, deeper coat under it...

Cheers,
M.
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Old 21st June 2018, 12:59 PM   #6200
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by ecdesigns View Post
Some examples of signed magnitude D/A converters are the Soekris DAC and the PCM1704 just to name a few of many.

...We end up with a 17 bit dual mono TDA1541A signed magnitude DAC, full scale current doubles to 8mA and resolution is doubled to 17 bits.
Hi John,

I found time to read the message No. 6116. The idea is good. This is called a segmented DAC.
Indeed, in this way it is possible to significantly reduce the interference from the conversion of the digit / analog near zero.
But to implement the 17-bit DAC on TDA1541 (similar to PCM1704) will not succeed.
The TDA1541 (A) chip accepts input data in only two formats: OB or TWC. In both formats, the MSB is interpreted as a signed bit.
In the PCM1704 chip, the conversion of numbers to the desired format is done inside the chip, and as a result, each of the two internal DACs operates in a dedicated 23-bit segment. Two 23-bit DACs, each working in its 23-bit segment, result in a single 24-bit DAC.
The size of each segment for the TDA1541 pair is 15 bits, since it is impossible to transfer a 16-bit natural number inside the TDA1541 (A) chip, only 15-bit. One bit (MSB) is inevitably spent on the sign of a number. Two DACs, each working on its own 15-bit segment, will result in a single 16-bit DAC.

Sincerely,
Serg
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