Building the ultimate NOS DAC using TDA1541A

Direct Interpolation DAC schematics

Hi, all

This is what you were all waiting for, schematics! As promised I will now (try) to post the first schematic diagram of the Direct Interpolation DAC. This is basically all you need, it's the digital interface (delay lines) between the I2S interface and a bunch of DAC's. The SPDIF to I2S interface (CS8412, CS8414) is published so often that I will skip that part. This interface will drive 2, 4 or 8 DAC's. Exact connections to the DAC's is in the schematics. If you only want to use a twin or quad DAC unused shift-registers can be left out. I will post some differential output-stages next (as soon as possible). Basically there are 2 approaches:

1) Differential version: Odd DAC numbers 1,3,5,7 are parallelled and are the +
output that feeds into the + input of a diff amp using an OP-amp or a
differential triode stage. The Even DAC numbers 2,4,6,8 are parallelled and
are the - output that feeds into the - input of a diff amp.

2) All parallell version: Connect all DAC outputs together and feed a passive
(resistor) I/V converter. IMPORTANT: do NOT use the 2 or 4 inverted
data outputs labelled ND32,ND48,ND56,ND40 but use D32,D48,D56,D40
as you don't want to invert any DAC outputs.

Attention! when parallelling DAC outputs with a passive I/V converter beware of the significant voltage increase over the I/V resistor causing (massive) distortion. A common value for a single DAC is 33 OHm, full scale current is 4mA so the voltage across the resistor is 132mV, this is already way to high according to the TDA1541A datasheet (+-25mV max. to ensure specified distortion figures). In order to not make things worse use the following indication:

TWIN DAC: 15 OHms (120mV)
QUAD DAC: 8.2 OHms (131.2mV)
OCTAL DAC: 3.9 OHms (124.8mV)

But I have a better solution for significantly reducing distortion in a tube output stage: Use a differential triode stage (ECC83 or so). Now use a separate resistor I/V stage for EACH DAC output (you can use low values here to keep distortion low). Then use a summing node to add all separate voltages together (one + node and 1 - node), this way you get higher output voltages AND lower resistor values. A 12 OHm resistor results in approx. 50 mV voltage drop, not bad. In an octal DAC you will still get 400mV to drive your tubes! of course you can also try an I/V transformer with multiple primary windings, or use single I/V transformers and put the outputs in series.
 

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quad dac

Hi tubee,

I had a look at the circuit, what happens with WS? as this signal determines when the sample occurs on the DAC output, this is important for interpolation. I am curious what you did with the oscillator PIN's 16 and 17, parallelling these pin's somtimes causes massive distortion. I use a separate 470pF 1% polystyrene on each DAC. Then you can assign 1 DAC as "master" then connect 100pF capacitors from pin16 of the master to each of the other 3 DAC's, check with an oscilloscope if all oscillators are in sync now. And the outputs? did you put them all in parallel? By the way I just posted my schematics, I think you could easily modify your quad DAC javascript:smilie :) , you could use the 74HC164 instead of the 74HC166 I used, but you need 12 of them for a quad DAC. You are always welcome to listen to the new DAC and the sonic resonators.
 
Hi ecdesigns,

Thanks for replying on my thread regarding balanced, paralleled DAC. The question I had for you was if you were ever planning to produce a DIY kit of your balanced, paralled 1541 DAC for the rest of us who don't know how to design a PCB, but are OK at soldering. Even if you don't, your design is so intriguing I'll probably get the bread board out and try to put it together myself!
 
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Even if you don't, your design is so intriguing I'll probably get the bread board out and try to put it together myself! [/B]


I agreed. I think quite a few of us will like to try it if there is a PCB. I think the PCB can also skip all the USB/SPDIF stuff in front too, as such functionalities are widely available, for example from dddac.
 
Correct me if I'm wrong. If you can get 400mV output with 8 chips, then with 20 chips, you can a full 1V output. You probably wouldn't need an active output stage (tube or opamp), if you have an active preamp. Right? I'm thinking simpler is better in this application. Doed's DDDAC doesn't require an active output stage because he gets 2V from his stacked 1543 chips, which may be related to the claimed purity/clarity in that DAC's sound.
 
Direct Interpolation DAC circuit boards

Hi, MGH

Thanks for your reply. Yes, I am designing circuit boards for this project. So other members can built this DAC or parts of it too because, it's fully modular, so you can experiment with different set-ups or modify your existing DAC. The photo of the quad DAC circuit board I posted earlier (the small module with 4 * TDA1541A on them) is in fact one of the modules of this new DAC (you need 2 of them for a octal DAC) . I am planning to make the following modules (circuit boards):

1) Differential schmitt trigger SPDIF driver (for low jitter)
2) Audio interface module 1: SPDIF to I2S
3) Audio interface module 2: USB to I2S
4) Direct Interpolation module (timing chain) for 2,4 and 8 DAC's that use I2S
5) DAC module with 4 * TDA1541A DAC's (this circuit board is ready)
6) DAC module with 4 * TDA1543
7) Differential output stage with OPA627 with/without Bessel filter
8) Differential triode / cascode output stage with/without Bessel filter
9) Main board for interconnecting the separate modules
10) Power supply with 3rd order line filter (note that every module already has voltage regulators built in for minimal interference, see photograph of the quad DAC module I posted, it has 12 regulators and 36 SMD bypass capacitors directly soldered to the chip's power supply PIN's).

Parallelling even more DAC's like the TDA1543 or TDA1541A is no problem, with the octal DAC version you can put 2 ore more DAC chips in parallel, for each DAC indicatad in the timing chain diagram I posted.

So if you have a lot of TDA1543's laying around you could use 8 of them in parallel for each of the mentioned DAC's, so the octal DAC get's 8 * 8 = 64 DAC's. Personally I think using 8 TDA1541A DAC's is more than sufficient, unless you use TDA1543 as this one has more distortion (see philips datasheets). As I mentioned before, getting a High output voltage is no proplem, with 33R resistors in an octal DAC you easily get 1V, but the problem is: the voltage at the DAC output must stay below 50mV (+-25) in order to keep distortion low. That's why I used an OP-amp I/V converter as it's input stays at virtual ground (0v) even at full scale current of 4mA or even higher.

But there is another solution: Use a very high quality OP-amp (OPA627 or AD equivalent) or a OP-amp using discrete components (perhaps a OP-amp using tubes) as I/V converter and a tube output stage, this way you get the best of both worlds: very low distortion and the tube sound you like so much.
 
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Re: Graphical example Direct Interpolation

-ecdesigns- said:
Hi all,

Perhaps a graphical representation of Direct Interpolation says more than a thousand words :) The example shows 2 DAC's. The blue block (and blue lines) indicate one sample (64 * BCK).

Ok,

So you delay half the sampletime, not a full like the pic on the prev page.

Think the old cambridge (think it was them? UK stuff anyway) cd players with 4 tda1541's worked like that. '16x oversampling' with a 7220 to get to 4 and 4 dacs with delays to get to '16'.

Think there a few posts on that too. :smash: Just search
 
Prototype Direct Interpolation DAC

Hi all,

For those who can't wait to hear this DAC, I will post a better photograph of the breadboard prototype so you have an example of how it can be done. I will post the differential output stage schematic diagrams part 1, very soon (my ancient DOS CAD system cannot export files). Then you got all necessary information to get soldering....Tip: by piggy-backing the 74HC166 (see photograph), the timing chain can be easilly build.
 

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Schematic diagram I/V diff amp

Hi, all

Here are the schematic diagrams of the I/V and differential amplifier stage part 1 that I promised.

Guido had a question about delaying samples:

A dual DAC: DAC 1 sample appears immideate, DAC2 sample 32BCK delay.

A quad DAC: DAC 1 sample appears immideate, DAC2 sample 32BCK delay,
DAC3 sample 16BCK delay. DAC4 sample 48BCK delay.

An octal DAC: DAC 1 sample appears immideate, DAC2 sample 32BCK delay,
DAC3 sample 16BCK delay. DAC4 sample 48BCK delay, DAC5 sample 8BCK delay, DAC6 sample 56 BCK delay, DAC7 sample 24 BCK delay and DAC8 sample 40BCK delay

So minumum sample delay is zero (DAC1), maximum delay is 56BCK pulses(DAC6) still less than 1 sample. All samples are delayed in the same manner (synchronous shiftregisters)

Hopefully this will clarify the delay "issue" ':)'






max. 48BCK delay for all samples and the octal DAC has max. 56 BCK pulses delay for all samples
 

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In my setup WS and Data has to be delayed in time, 4 clockcycles/ dac whith four dacs. Want to tie all outputs together after 4 I/V resistors/dac and tubes (allen bradleys), or maybe use the Pedja's AD844 output stage, an IC I/V with many good reactions on the sound of it. The AD844 is used in an other implementation with Pedja's I/V.

The interpolation with 4 dacs schematic looks very simple, yours Ecdesigns is more complicated, with more logic, and i want it as simple as possible to reduce extra's (jitter?) I think this design is allmost the same as Cambridge used, not sure, only they kept SAA7220, thus 16 times oversampled (4*4)

Btw wat clock do you use Ecdesigns, are you familiar with Guido's or Elso's creations?
 
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Why using so many chips ?

Just contemplated a bit on the usage of so many shift registers as the only thing each IC does is delaying the signal for 8 BCK clock cycles and than give an output. Why not divide the clock by 8 than and use one SHIFT step ????

So I put a quick circuit up and this should be giving the same result as the proposed circuit with 14 x 74HC166, with advantage, that VHC logic can be used, less inputs are loaded on the BCK clock (in stead of 14 inputs now 1) and the PCB design will be easier and smaller, so now a very small (if done in SMD) PCB is possible, so it can be implemented more easily in existing DAC systems (like my DAC-Modules) as a small add-on, directly where the I2S signals are entering the DAC chips.

Just my 2 cents ..... not tested and 100% thought through, but just have a look at the basic idea ...


doede


PS: mmmhh, already see that this will not work of course for DATA :cannotbe:

For the WS it should work though....

I put on a "new Circuirt" idea. OK, the gain is not so huge anymore, only "saving" 5 IC's.....
 

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Hi, dddac,

Thanks for your reply.

If you read my explanations of the Direct Interpolation DAC in my previous posts carefully and look at the graphic representation picture called dip.jpg (twin DAC example), you will see that I have to shift the entire datastream realtime including wordselect, otherwise my concept won't work. The DAC's don't "know" that they receive a different signal, they just put the sample on their output after the trailing edge of WS.

By creating a true (bitwise) digital delay of both data and WS I can move the "cloned" samples around in the time domain with the exact same data as the original sample. These "clone" samples are then placed on specific points in the 64BCK time window (8,16,24,32,40,48 and 56BCK for an octal DAC version). Remember that I make "clone" samples of one sample only. Believe me, if I could have done it easier I certanly would, it has to be a true bitwise double digital delay line, one for WS and one for DATA.

A second issue is fully synchronous operation (all actions are synced with BCK)
for both data and WS signal to ensure that the realtime audio bitstream is not disrupted in any way, so the circuit must be fully symetrical for both WS and DATA. I specially used high speed 74HC166 synchronous shiftregisters and gates for this purpose, 4000 series are way too slow at 5v. I have already routed the circuit board for the timing chain today so "complexity" is no problem. Since the timing chain had to be universal for twin, quad and octal DAC's it got 2 extra shiftregisters. If you could only hear it's sound, you would gladly invest in a few cheap HCTTL chips. And when you look at the picture called prototype.jpg, it's not that complicated:).
 
simplifying timing chain

hi, dddac,

I have tried the setup you proposed, the idea is very good (because WS is just a symetrical squarewave and the databits are a continuously varying bitstream), but the VHC4040 (sorry I mixed this one up with CD4040:xeye:), is an asynchronous binary counter that delays the clock for the following shiftregister VHC74164. When the VHC4040 is replaced by a synchronous binary counter 74VHC161 it would solve this problem. Correct me if I am wrong but the BCK clock loading in your design is 8*74VHC164 (data delay), 1*VHC4040(divide by 8 counter), and 1*74VHC164 (WS delay). I used the same timing chain both for WS and DATA to make absolutely sure the audio bitstream is not disrupted. As far as SMD is concerned, this would make this project more difficuilt to build for other DIY members, unless they buy a complete assembled circuit board.
 
Clocks, jitter

Hi tubee,

Thanks for your reply.,

I think the total delay is 16BCK cycles, that way there is a difference in individual sample length, I tried this as well but it didn't sound very well. In my design all subsamples have exactly the same length:

32BCK for a twin DAC, 16BCK for a quad DAC and 8BCK for the octal DAC.

Since the Cambridge model used the SAA7220 / oversampling, it's a different system.

I tried self made stranded copperwire resistors (mobius loop using spiderweb winding to reduce capacitance). These sound very natural and exeptionally clear.

I tried all kinds of setup for the I/V stage. Passive resistor stages are problematic because a voltage drop of more then 50mV across them already compromizes distortion figures. So you have to work with very low voltages that are prone to noise and interference signals. Furthermore the following amplifier needs relatively high gain, reducing the bandwith and phase response. You also need capacitors and / or coils in the signal path (phase).

I finally settled for the high quality OP-amp version that I posted. The output of the DAC is connected to the OP-amp - input (virtual ground) so the voltage drop problem is solved keeping distortion very low. The OPA627 really sounds very good (just have a look at the reviews on this chip on the internet). The only "problem" is it's high price.

I have already routed the circuit board for the Direct Interpolation DAC timing chain. It's smaller than the DAC TDA1541A module I posted, just hook up some wires to the 4 DAC's and you're ready to go. I think it's important to go for the best sound quality, not because a circuit looks simple. The timing chain is fully synchronous and therefore add's no jitter. The 74HC166 types are very fast, faster than the 74HCT166 version.

As far as clocks are concerned (jitter) I make sure jitter is reduced by increasing the slew rate of the SPDIF signal right at the signal source (I use a schmitt trigger 74HC14 with a 680 OHm resistor between input and output and a 10nF capacitor between the SPDIF signal and the schmitt trigger input. Then the schmitt trigger output is fed to a differential RS422 driver chip (DS8922N) this RS422 chip is also ideal for buffering I2S signals. This way I start off with a clean SPDIF signal right at the source.

This makes more sense then trying to correct a jittery signal afterwards. When I put the MCLK signal of the CS8412 on my oscilloscope it looks rock solid (no haze at the trailing edge of the pulses. A very accurate frequency counter shows a rock solid 2.822400 MHz (last digit doesn't change at all). Remember, when there is jitter on the SPDIF signal, this is even enhanced by the receivers PLL circuitry, then it get's very difficult to correct this. The best method of course is using the I2S signal directly from the transport, but this isn't always possible (warranty).
 
Re: simplifying timing chain

-ecdesigns- said:
.......... As far as SMD is concerned, this would make this project more difficuilt to build for other DIY members, unless they buy a complete assembled circuit board............


Hi.

I would second that !
While I can solder/desolder smt devices and they do make for smaller, neater final pcbs, I prefer to work with through-hole devices.
2 reasons ...

Easier to breadboard
Easier to see

So if a PCB is to be produced, I would prefer TH

Andy
 
Hi bernhard,

Thanks for your reply,

No I use Direct Interpolation. The new samples are fixed in the time domain in a way that all subsamples have exactly the same length (if the length per sample would vary then you are absolutely right). So in this system no jitter occurs, this is also verified by measurements and listening sessions. The samples are also in sync with BCK (44.1KHz for all DAC chips). If my system had jitter it would be definitly audible on my sonic resonator speakers as these reconstruct recording room acoustics and depend on perfect phase properties. The slightest error immediately blurs the image. It is as if you put a "magnifying glass" on the audio signal. Furthermore I use a standard NOS DAC as Reference and toggle between the two. as I mentioned in earlier posts (this certainly has no jitter as MCLK is rock solid). The Direct Interpolation DAC gives a very clean natural sound with an abundance of detail, even the bass and midrange have improved. The reference DAC simply can't reproduce these because details are covered up by the well known ultrasonic interference. When this interference is removed by shifting the mirror image up to a higher frequency and enhance resolution as my Direct Interpolation DAC does, the covered up details appear clearly audible, and you start hearing details in a recording very clearly. On one test CD I could clearly hear the artist breathing between singing (CD: steppin, track: Will it go round in circles), I am very familiar with this recording (part of my test CD collection) and I never heard that so clearly with my reference NOS-DAC. So it's a significant improvement verified by measurements and listening sessions. Please read my other posts explaining Direct Interpolation carefully.

As linearity is concerned, optimalisation can still be achieved by changing individual I/V stage gain to get a logarithmic response. The timing chain needs no modification for this
 
FIRST OSCILLOGRAMS D-I NOS-DAC!

Hi all,

Here are the first oscilloscope pictures of the Direct Interpolation NOS-DAC, compared to a reference NOS-dac

Note it is very difficult to photograph real-time audio signals on an oscilloscope, so this is only to give an impression.

Upper trace: Direct Interpolation NOS-dac (Quad version) unfiltered!

Lower trace: Reference NOS-dac unfiltered!

Notice the difference in resolution!
 

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