Hi Art,
DJA works for all sample rates, the one connected to my masterclock operates at 11.2896 MHz.
One function of the DJA is clock rectifier. When clock signal goes positive, it clocks connected load through damping resistor R1 (47R). When clock signal goes negative, D3 ... D6 stop conducting (disconnect load from clock signal). This reduces the time the load is connected to the clock, and contributes to jitter reduction. Since the output signal of my 4-crystal clock varies between +4V and -4V, clock rectifier is needed in order to feed flip-flop U5.
Clock signal level "0" is determined by the bias voltage across C26 and R6. Load input capacitance is gently discharged through R5 (270R) until it reaches bias voltage level (0.6V), this reduces the effects of ground bounce and thus reduces jitter.
C26 and R6 form an integrator. They act as "smoothing cap" for the rectified clock signal. Derived bias voltage level depends on R5 and R6. For TDA1541A I use 0.8V bias voltage (must be measured with oscilloscope). Clock signal varies between 0.8 and 2.4V (1.6Vpp), this way the amount of energy dumped on the chip substrate (input capacitance) is reduced. This in turn reduces on-chip jitter.
Attenuator: Voltage drop across D3 ... D6 equals approx. 4 x 0.4V = 1.6V. Input voltage equals 4V, so signal amplitude equals approx. 4 - 1.6 = 2.4V.
When using an external bias voltage, power supply noise and interference will be added to the clock signal, degrading performance.
Finally the dynamically varying bias voltage (varies with clock jitter / clock duty cycle) might contribute to further jitter reduction by manipulating exact moment of triggering, but this function is debatable.
Similar circuit is used for feeding bit reclocker U5. The 4-crystal clock buffered output signal swings between +4V and -4V (8Vpp). So the clock signal needs to be rectified before feeding it to U5 clock input. DJA output signal varies between 0.4V (bias voltage) and 4 - 1 = 3V. Signal amplitude equals 2.6Vpp. Similar to the DJA for the bit clock, this master clock DJA reduces ground-bounce in U5 input circuit, reducing jitter.
DJA works for all sample rates, the one connected to my masterclock operates at 11.2896 MHz.
One function of the DJA is clock rectifier. When clock signal goes positive, it clocks connected load through damping resistor R1 (47R). When clock signal goes negative, D3 ... D6 stop conducting (disconnect load from clock signal). This reduces the time the load is connected to the clock, and contributes to jitter reduction. Since the output signal of my 4-crystal clock varies between +4V and -4V, clock rectifier is needed in order to feed flip-flop U5.
Clock signal level "0" is determined by the bias voltage across C26 and R6. Load input capacitance is gently discharged through R5 (270R) until it reaches bias voltage level (0.6V), this reduces the effects of ground bounce and thus reduces jitter.
C26 and R6 form an integrator. They act as "smoothing cap" for the rectified clock signal. Derived bias voltage level depends on R5 and R6. For TDA1541A I use 0.8V bias voltage (must be measured with oscilloscope). Clock signal varies between 0.8 and 2.4V (1.6Vpp), this way the amount of energy dumped on the chip substrate (input capacitance) is reduced. This in turn reduces on-chip jitter.
Attenuator: Voltage drop across D3 ... D6 equals approx. 4 x 0.4V = 1.6V. Input voltage equals 4V, so signal amplitude equals approx. 4 - 1.6 = 2.4V.
When using an external bias voltage, power supply noise and interference will be added to the clock signal, degrading performance.
Finally the dynamically varying bias voltage (varies with clock jitter / clock duty cycle) might contribute to further jitter reduction by manipulating exact moment of triggering, but this function is debatable.
Similar circuit is used for feeding bit reclocker U5. The 4-crystal clock buffered output signal swings between +4V and -4V (8Vpp). So the clock signal needs to be rectified before feeding it to U5 clock input. DJA output signal varies between 0.4V (bias voltage) and 4 - 1 = 3V. Signal amplitude equals 2.6Vpp. Similar to the DJA for the bit clock, this master clock DJA reduces ground-bounce in U5 input circuit, reducing jitter.
Thank you John, you were really helpful.
Now I'm going to build my DAC following your suggestions.
I'd like not to use a diy PCB. My idea is to use a copper board for PCBs, but with no traces at all, only a ground plane. Thus the 14 filter capacitors will be soldered directly on the ground plane, and the same will happen for all the other components that shall be routed to ground (pin 5, pin 14, as well as R6, R13, and R14 of the I2S signal attenuator/DJA). This way connections to ground are spread all over the ground plane. I'm afraid that this simplicistic approach could not be optimal as regards performances. What's the bad (if any) ? I've seen that in your board the 14 capacitors have a short dedicated route to pin 5. Is this a a better solution, and why?
Best regards.
Paul
Now I'm going to build my DAC following your suggestions.
I'd like not to use a diy PCB. My idea is to use a copper board for PCBs, but with no traces at all, only a ground plane. Thus the 14 filter capacitors will be soldered directly on the ground plane, and the same will happen for all the other components that shall be routed to ground (pin 5, pin 14, as well as R6, R13, and R14 of the I2S signal attenuator/DJA). This way connections to ground are spread all over the ground plane. I'm afraid that this simplicistic approach could not be optimal as regards performances. What's the bad (if any) ? I've seen that in your board the 14 capacitors have a short dedicated route to pin 5. Is this a a better solution, and why?
Best regards.
Paul
Hi Sandor,
TDA1541A-MK2 board lay-out and GND routing was extensively tested / emulated using a practical prototype test setup.
This is done for very good reason, I already explained it on this thread. It is done to prevent supply currents running through the GND plane from mixing with 14 decoupling cap GND returns. This way the bit currents of the 6 MSBs stay as clean as possible.
The decoupling caps are connected to the active divider outputs that carry the 6 MSB binary weighted currents. When injecting ripple current on the decoupling cap GND return, it will add to the bit currents causing dynamic bit errors (bit currents vary dynamically with the interference signals). The decoupling caps cannot decouple these interference currents because their reference (GND) varies dynamically.
TDA1541A-MK2 board lay-out and GND routing was extensively tested / emulated using a practical prototype test setup.
This is done for very good reason, I already explained it on this thread. It is done to prevent supply currents running through the GND plane from mixing with 14 decoupling cap GND returns. This way the bit currents of the 6 MSBs stay as clean as possible.
The decoupling caps are connected to the active divider outputs that carry the 6 MSB binary weighted currents. When injecting ripple current on the decoupling cap GND return, it will add to the bit currents causing dynamic bit errors (bit currents vary dynamically with the interference signals). The decoupling caps cannot decouple these interference currents because their reference (GND) varies dynamically.
They are here, they are here!
At last, the resistance wires arrived! Two to three months and a very expensive shipping method, directly from Germany.
Here are photos from my D1 DAC with variable I/V resistor, with parallel DIY honeycomb resistors.
Picasa Web Albums - mauricio
Picasa Web Albums - mauricio
This 100R/m wire is very, very thin.
Cheers,
M.
At last, the resistance wires arrived! Two to three months and a very expensive shipping method, directly from Germany.
Here are photos from my D1 DAC with variable I/V resistor, with parallel DIY honeycomb resistors.
Picasa Web Albums - mauricio
Picasa Web Albums - mauricio
This 100R/m wire is very, very thin.
Cheers,
M.
At last, the resistance wires arrived! Two to three months and a very expensive shipping method, directly from Germany.
Here are photos from my D1 DAC with variable I/V resistor, with parallel DIY honeycomb resistors.
Picasa Web Albums - mauricio
Picasa Web Albums - mauricio
This 100R/m wire is very, very thin.
Cheers,
M.
So at highest volume setting you have those marvellous honeysound resistors while at low volume setting you are using a standard ALPS pot as I/V resistor.
Did you measure the pot resistance at average listening level ?
It is much below those 500 ohms.
At -6 dB your pot has 500 ohms.
Any bells ringing ?
Why not use a rotary switch together with diy resistors ?
A few hundred gramms airmail registered letter cost 8 EUR from Germany worldwide.
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Hi dear Bernhardt,
It is always nice to hear from you. Your general mood is refreshing for this XXI century world of us.
As I have stated many times, I only need three steps (around +/-6db) between loudest and softest recorded files to get comfortable SPL. I could make a DIY stepped attenuator but I don't have time. Mean I/V reads 324R. I don't detect any significant HF noise. The neighbour's dog has not complained.
Conrad sent the wire on a big carton box and asked around EU30 or so for the shipment that took 2 weeks (since departure to arrive).
I won't qualify the German's ability to trade, publicly...
Cheers,
M.
It is always nice to hear from you. Your general mood is refreshing for this XXI century world of us.
As I have stated many times, I only need three steps (around +/-6db) between loudest and softest recorded files to get comfortable SPL. I could make a DIY stepped attenuator but I don't have time. Mean I/V reads 324R. I don't detect any significant HF noise. The neighbour's dog has not complained.
Conrad sent the wire on a big carton box and asked around EU30 or so for the shipment that took 2 weeks (since departure to arrive).
I won't qualify the German's ability to trade, publicly...
Cheers,
M.
Hi Maxlorenz,
The I/V resistor is very important with passive I/V conversion. Paralleling an ALPS potentiometer works, but might not be optimal.
Using multiple I/V resistors with switches isn't optimal either. Every switch added to the signal path can degrade performance.
When using multiple DAC chips in parallel, the following "digital" volume control technique may be interesting.
The DAC output amplitude increases as more DAC chips are placed in Parallel (full-scale current rises). So it should be possible to feed zeroes into selected DAC chips so they won't contribute to the ac output signal. No resolution is lost as each DAC outputs 16 bits, regardless of volume setting.
This way one can achieve lossless digital volume control using a fixed high quality I/V resistor.
Volume control could be achieved by adding an AND gate (74HC08) in series with each DATA input of each DAC chip. Input #1 goes to DATA output of the source, input #2 goes to a switch to toggle logic "0" or "1". The output is connected to the DAC chip DATA input.
By putting a "0" on the AND gate #2 input, the connected DAC would not output ac signal while maintaining correct bias voltage. When putting a "1" on the AND gate #2 input, the source DATA passes and the connected DAC chip will contribute to the combined output signal.
When putting zero on all DAC chip AND gates, muting is achieved.
Example with 8 x TDA1543 and 100R I/V resistor:
muting > 0 0 0 0 0 0 0 0, no signal
vol 1 > 0 0 0 0 0 0 0 1, 250mV
vol 2 > 0 0 0 0 0 0 1 1, 500mV
Vol 3 > 0 0 0 0 0 1 1 1, 750mV
Vol 4 > 0 0 0 0 1 1 1 1, 1V
Vol 5 > 0 0 0 1 1 1 1 1, 1.25V
Vol 5 > 0 0 1 1 1 1 1 1, 1.5V
Vol 6 > 0 1 1 1 1 1 1 1, 1.75V
Vol 7 > 1 1 1 1 1 1 1 1, 2V
The I/V resistor is very important with passive I/V conversion. Paralleling an ALPS potentiometer works, but might not be optimal.
Using multiple I/V resistors with switches isn't optimal either. Every switch added to the signal path can degrade performance.
When using multiple DAC chips in parallel, the following "digital" volume control technique may be interesting.
The DAC output amplitude increases as more DAC chips are placed in Parallel (full-scale current rises). So it should be possible to feed zeroes into selected DAC chips so they won't contribute to the ac output signal. No resolution is lost as each DAC outputs 16 bits, regardless of volume setting.
This way one can achieve lossless digital volume control using a fixed high quality I/V resistor.
Volume control could be achieved by adding an AND gate (74HC08) in series with each DATA input of each DAC chip. Input #1 goes to DATA output of the source, input #2 goes to a switch to toggle logic "0" or "1". The output is connected to the DAC chip DATA input.
By putting a "0" on the AND gate #2 input, the connected DAC would not output ac signal while maintaining correct bias voltage. When putting a "1" on the AND gate #2 input, the source DATA passes and the connected DAC chip will contribute to the combined output signal.
When putting zero on all DAC chip AND gates, muting is achieved.
Example with 8 x TDA1543 and 100R I/V resistor:
muting > 0 0 0 0 0 0 0 0, no signal
vol 1 > 0 0 0 0 0 0 0 1, 250mV
vol 2 > 0 0 0 0 0 0 1 1, 500mV
Vol 3 > 0 0 0 0 0 1 1 1, 750mV
Vol 4 > 0 0 0 0 1 1 1 1, 1V
Vol 5 > 0 0 0 1 1 1 1 1, 1.25V
Vol 5 > 0 0 1 1 1 1 1 1, 1.5V
Vol 6 > 0 1 1 1 1 1 1 1, 1.75V
Vol 7 > 1 1 1 1 1 1 1 1, 2V
In this special case the I/V res will always be large compared to the res of the switch, so it won't degrade sound no more than using the switch elsewhere.
- 60 dB attenuation range could be a problem though.
Is the DJA circuit audible?
Hi John,
Your DJA concept has always appeared theoretically possible (and quite clever) to me, but it was apparent that the specific implementation details are critical. The first thing to make sure of is that the effect of the jitter induced duty-cycle variations of the DJA circuit actually present a net jitter reducing and not a net jitter increasing effect on the DAC conversion instants.
Assuming that you lack access to a high-resolution jitter analyzer my question is, what do your ears tell you with the DJA in, versus with the DJA out?
Hi John,
Your DJA concept has always appeared theoretically possible (and quite clever) to me, but it was apparent that the specific implementation details are critical. The first thing to make sure of is that the effect of the jitter induced duty-cycle variations of the DJA circuit actually present a net jitter reducing and not a net jitter increasing effect on the DAC conversion instants.
Assuming that you lack access to a high-resolution jitter analyzer my question is, what do your ears tell you with the DJA in, versus with the DJA out?
dear friends, here is a cheapo version of much envied EC's R i/v
Have no access here of coated resistance wire, made from 39ohms 5W white brick R's, thick & thin semi-transparent double tapes and teflon plumbing tape.
Not fully bench marked yet, but it sounds better than phillips metal film, about 50/50 with Takman carbon film-but not yet decided
@ EC, do you think this method achieved goals of non-inductance, high wattage, etc? Appreciate your opinion
Thanks
TeguhPS
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![IMGHTTPDEAD]](/community/proxy.php?image=http%3A%2F%2F%5BIMGHTTPDEAD%5Dhttp%3A%2F%2Fimg8.imageshack.us%2Fimg8%2F8987%2Friv8s.jpg%5B%2FIMGHTTPDEAD%5D&hash=44adba6d8d9fa7d4d1c40506eb441fa5)
![IMGHTTPDEAD]](/community/proxy.php?image=http%3A%2F%2F%5BIMGHTTPDEAD%5Dhttp%3A%2F%2Fimg63.imageshack.us%2Fimg63%2F7172%2Friv15s.jpg%5B%2FIMGHTTPDEAD%5D&hash=9f0135fff68c9e29fa345a6046aced97)
Have no access here of coated resistance wire, made from 39ohms 5W white brick R's, thick & thin semi-transparent double tapes and teflon plumbing tape.
Not fully bench marked yet, but it sounds better than phillips metal film, about 50/50 with Takman carbon film-but not yet decided
@ EC, do you think this method achieved goals of non-inductance, high wattage, etc? Appreciate your opinion
Thanks
TeguhPS
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Hi ide2003,
Non-inductive construction requires canceling of magnetic fields produced by the current running through the wire. This can be achieved with an Aryton Perry winding method:
Ayrton-Perry winding - Wikipedia, the free encyclopedia
Or a Mobius loop or comparable construction:
Möbius resistor - Wikipedia, the free encyclopedia
If you are using a non-folded single wire, the construction is still inductive.
The Mobius / honeycomb I/V resistors basically consist of a folded wire (mobius loop). Piece of 5 meter resistance wire (100R / meter) is folded leaving 2.5 meters of wire with connections on one side.
Next, the fold is attached to the frame. Then two wires are wound simultaneously side-by side (same distance between the wires).
Since I use an odd number of petals (11) and always skip 3 petals, honeycomb winding pattern is formed, minimizing self capacitance.
here is a link explaining resistor noise
Resistor Types--Does It Matter?
In order to prevent unwanted inter action between I/V resistor and connected load(s), suitable output buffer is required. I use 500R passive I/V resistor with TDA1541A (2Vpp signal across the I/V resistor) together with a JFET current buffer to minimize ac / dc voltage at the DAC output. Without buffer, output impedance would be approx. 500R. By using complementary JFET output buffer, output impedance could be lowered to approx. 22 Ohms.
Non-inductive construction requires canceling of magnetic fields produced by the current running through the wire. This can be achieved with an Aryton Perry winding method:
Ayrton-Perry winding - Wikipedia, the free encyclopedia
Or a Mobius loop or comparable construction:
Möbius resistor - Wikipedia, the free encyclopedia
If you are using a non-folded single wire, the construction is still inductive.
The Mobius / honeycomb I/V resistors basically consist of a folded wire (mobius loop). Piece of 5 meter resistance wire (100R / meter) is folded leaving 2.5 meters of wire with connections on one side.
Next, the fold is attached to the frame. Then two wires are wound simultaneously side-by side (same distance between the wires).
Since I use an odd number of petals (11) and always skip 3 petals, honeycomb winding pattern is formed, minimizing self capacitance.
here is a link explaining resistor noise
Resistor Types--Does It Matter?
In order to prevent unwanted inter action between I/V resistor and connected load(s), suitable output buffer is required. I use 500R passive I/V resistor with TDA1541A (2Vpp signal across the I/V resistor) together with a JFET current buffer to minimize ac / dc voltage at the DAC output. Without buffer, output impedance would be approx. 500R. By using complementary JFET output buffer, output impedance could be lowered to approx. 22 Ohms.
hi EC, thanks for your opinion. You're right, it is the non folded single wire I've used. Sorry for prematurely calling this your R i/v version.
After reading your & ayrton-perry's info, it means that I should fold the wire in half length first then laying it in 'zig-zag' manner on top of my double tape (while taking care so no wires touching each others), cmiiw.
After R i/v I connecting it directly to tube grid, is your buffer still required?
TIA
TeguhPS
After reading your & ayrton-perry's info, it means that I should fold the wire in half length first then laying it in 'zig-zag' manner on top of my double tape (while taking care so no wires touching each others), cmiiw.
After R i/v I connecting it directly to tube grid, is your buffer still required?
TIA
TeguhPS
Hi 2003,
Yes, but insulate the resistance wire first. You can use a small paintbrush and suitable lacquer to coat the resistance wire. Use multiple coatings in order to ensure reliable insulation layer.
It would not be required, provided wiring is kept very short and load capacitance is reduced to minimum.
Yes, but insulate the resistance wire first. You can use a small paintbrush and suitable lacquer to coat the resistance wire. Use multiple coatings in order to ensure reliable insulation layer.
It would not be required, provided wiring is kept very short and load capacitance is reduced to minimum.
Hi EC, thanks. I think I still have those R39 white bricks. will try another pair & show them when ready
also from R i/v to grid my wiring is far from short..about 8" , so I might need your buffer after all
@nico, dunno the wattage here, but it can be as high as your double tapes can take the heat, cmiiw, may be the amber colored kapton tapes will be better
regards
TeguhPS
also from R i/v to grid my wiring is far from short..about 8" , so I might need your buffer after all
@nico, dunno the wattage here, but it can be as high as your double tapes can take the heat, cmiiw, may be the amber colored kapton tapes will be better
regards
TeguhPS
Hi nicoch46
If I am correct the 26 triode requires 1.5V / 1A for filament.
Why not try a 1.5V alkaline D-cell (average 12Ah), or rechargeable 2V lead-acid battery for the filament. It would solve the filament induced hum for sure. For 2V power supply you would need 0.5 Ohms series resistor with approx. 1 ... 5W power rating.
Non-inductive wire wound Mills resistors would be suitable.
If I am correct the 26 triode requires 1.5V / 1A for filament.
Why not try a 1.5V alkaline D-cell (average 12Ah), or rechargeable 2V lead-acid battery for the filament. It would solve the filament induced hum for sure. For 2V power supply you would need 0.5 Ohms series resistor with approx. 1 ... 5W power rating.
Non-inductive wire wound Mills resistors would be suitable.
Hi Ken,
The DJA is just one of many circuits that affect jitter. When source jitter is below say -100dB @ 10 Hz and -180dB @ 1 KHz, the DAC chip contributes highest jitter by far.
SD-player Example:
3-crystal masterclock jitter, 1ps rms
Synchronous bit reclocker jitter contribution, 10ps rms (2.7ns propagation delay, approx. 27ps pp jitter)
TDA1541A jitter contribution, 70ps rms (20ns propagation delay, approx. 200ps pp jitter)
Then cumulated jitter equals approx. 81ps rms.
Max. allowable jitter for 44.1 / 16 NOS equals 173ps pp or 61ps rms (1 / fs / 2^n / 2).
So without any further corrections like with the DJA, it should be possible to get close to this target value.
By adding the DJAs, I can meet 61ps rms spec, thus enabling the possibility of resolving true 16 bit resolution.
Note that this is a unique concept that completely eliminates SPDIF / USB digital audio source, interlink and receiver jitter. Yet it's still quite difficult to meet 44.1 / 16 NOS specs.
Here is a calculation for max. allowable jitter in a 192 / 24 playback system with 8* oversampling:
1 / 8fs / 2^24 / 2 = 1 / 1536000 / 2^24 / 2 = 19.4 femto seconds (6.85 femto seconds rms).
Digital audio, unlike analogue audio consists of a sequence of pulses. The pulse energy ultimately determines the amount of power fed to the speakers and thus the actual cone displacement.
The pulse energy depends on pulse amplitude (sample value) and duty cycle. Jitter changes the duty cycle of each sample, minute duty cycle differences are sufficient to mask LSBs.
So despite the fact that timing deviations (jitter) are extremely small compared to the audio range, their effect on pulse energy can easily lead to reduced bit resolution.
The DJA is just one of many circuits that affect jitter. When source jitter is below say -100dB @ 10 Hz and -180dB @ 1 KHz, the DAC chip contributes highest jitter by far.
SD-player Example:
3-crystal masterclock jitter, 1ps rms
Synchronous bit reclocker jitter contribution, 10ps rms (2.7ns propagation delay, approx. 27ps pp jitter)
TDA1541A jitter contribution, 70ps rms (20ns propagation delay, approx. 200ps pp jitter)
Then cumulated jitter equals approx. 81ps rms.
Max. allowable jitter for 44.1 / 16 NOS equals 173ps pp or 61ps rms (1 / fs / 2^n / 2).
So without any further corrections like with the DJA, it should be possible to get close to this target value.
By adding the DJAs, I can meet 61ps rms spec, thus enabling the possibility of resolving true 16 bit resolution.
Note that this is a unique concept that completely eliminates SPDIF / USB digital audio source, interlink and receiver jitter. Yet it's still quite difficult to meet 44.1 / 16 NOS specs.
Here is a calculation for max. allowable jitter in a 192 / 24 playback system with 8* oversampling:
1 / 8fs / 2^24 / 2 = 1 / 1536000 / 2^24 / 2 = 19.4 femto seconds (6.85 femto seconds rms).
Digital audio, unlike analogue audio consists of a sequence of pulses. The pulse energy ultimately determines the amount of power fed to the speakers and thus the actual cone displacement.
The pulse energy depends on pulse amplitude (sample value) and duty cycle. Jitter changes the duty cycle of each sample, minute duty cycle differences are sufficient to mask LSBs.
So despite the fact that timing deviations (jitter) are extremely small compared to the audio range, their effect on pulse energy can easily lead to reduced bit resolution.