Go Back   Home > Forums > >
Home Forums Rules Articles diyAudio Store Blogs Gallery Wiki Register Donations FAQ Calendar Search Today's Posts Mark Forums Read

Digital Line Level DACs, Digital Crossovers, Equalizers, etc.

Building the ultimate NOS DAC using TDA1541A
Building the ultimate NOS DAC using TDA1541A
Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 27th June 2007, 09:09 PM   #1591
anatech is offline anatech  Canada
diyAudio Moderator
 
anatech's Avatar
 
Join Date: Jun 2004
Location: Georgetown, On
Building the ultimate NOS DAC using TDA1541A
Hi Christer,
The only thing I'll add to the excellent points you've made is that I've had enough SanDisk failures to be suspicious of the brand, and the technology. And those were used for data transfer (still babies when they died) and digital cameras (again, babies and DOA's). I'm not fan of these, but I would be if they were more reliable. We tried doing phone system programming backups with them. Now we when back to saving files on the laptop HD.

-Chris
__________________
"Just because you can, doesn't mean you should" my Wife
  Reply With Quote
Old 27th June 2007, 09:15 PM   #1592
Christer is offline Christer  Sweden
diyAudio Member
 
Join Date: Sep 2002
Location: Sweden
Chris,

are you referring to Sandisk only, or flash technology in general? And do you mean device failures, that makes them unusable or unreliable, or do you mean they are unreliable as in having many read-/write errors?

I have far to little experience of the technology. The only one being the Sandisk card in my digital camera, which has worked well so far.
  Reply With Quote
Old 27th June 2007, 09:50 PM   #1593
ecdesigns is offline ecdesigns  Netherlands
diyAudio Member
 
Join Date: May 2006
Location: Holland
Default DI DAC USB specification

Hi arielpuri,

Thanks for your reply [post #1581]


Quote:
is USB 1.x enough quick for DIx DACs?
Yes, the PCM2706 used, works with usb 1.1 and is compatible with USB2.0. It needs no drivers.
  Reply With Quote
Old 28th June 2007, 04:07 AM   #1594
anatech is offline anatech  Canada
diyAudio Moderator
 
anatech's Avatar
 
Join Date: Jun 2004
Location: Georgetown, On
Building the ultimate NOS DAC using TDA1541A
Hi Christer,
Complete failures. Cards that formatted fine and failed to capture data. More headaches than I care to mention. All with Sandisk. Some failures with the digital camera. Nikon and the cameras checked fine by Nikon. Other cards worked great.

I haven't bothered to try lately. I imagine they must have improved them. I know this because they are still in business. Could have been a bad batch I guess.

-Chris
__________________
"Just because you can, doesn't mean you should" my Wife
  Reply With Quote
Old 2nd July 2007, 07:43 AM   #1595
Brent Welke is offline Brent Welke  Canada
diyAudio Member
 
Join Date: Jun 2004
Location: Victoria, BC
Default I2S Reclocker - How Does It Work?

Hi ECDesigns,

I have added your reclocker http://www.diyaudio.com/forums/attac...amp=1160403522
to one of my single TDA1534 chip DACs. Thank you for sharing, it was a fun evening.

The DAC was built a week ago from all new parts and is still breaking in. I added a jumper/switch on the board so I can switch on/off the reclocker. The TDA1534 either has the BCK signal direct from the PCM2706/7 chip or from the reclocker.

There is a noticeable difference in sound between the two settings. Reclocked BCK is the setting I prefer, at times it seems to be missing something I enjoyed from the direct BCK setting. I likely need more time to come to grips with what I am hearing or not hearing. At a later date I will comment on how it affects the sound. I am trying to not let DIY building emotions affect my judment so much

The point of my posting is to ask you (or anyone who can) to help me understand the reclocking. From looking at the logic I see that the BCK signal from the PCM2706/7 is delayed by one 48MHz clock cycle while the DATA and WS signals are untouched.

To me this makes sense to allow the WS and DATA signals to settle out of the jitter zone and BCK is now clocked from the 48MHz clock which has less jitter then from the PCM2706/7.

But I don't understand the relationship between the 48MHz clock and BCK from the PCM2706/7. I wish I knew how the PCM produces BCK from the 12MHz clock. I found the SPACT patent but it is too broad in scope to tell me much http://www.google.com/patents?id=8tg...spact#PPA26,M1 .

If 48MHz was evenly divisible by BCK and synchronous to it then it would make perfect sense to me. But since they don't seem to be then how can they act together to produce a correct reclocked BCK signal without beating or at all?

Please enlighten me, this has been bugging me for a week now, I can not get it out of my mind
  Reply With Quote
Old 2nd July 2007, 08:27 PM   #1596
Onnosr is offline Onnosr  Netherlands
diyAudio Member
 
Join Date: Aug 2006
Dear John (ECdesigns)

I tried the dem osc running on 705,6 khz (instead of 352,8)
coupled direct via 470 pf to pin 16 (pin 17 0.2 mf to agn)

soundstage is more massive imho

Pse give it a try and tell us your outcome.

the tda1541a is able to handle that freq.

regards.

Onno
  Reply With Quote
Old 2nd July 2007, 10:33 PM   #1597
ecdesigns is offline ecdesigns  Netherlands
diyAudio Member
 
Join Date: May 2006
Location: Holland
Default Reclocking

Hi Brent Welke,

Thanks for your reply [post # 1595]


Quote:
The point of my posting is to ask you (or anyone who can) to help me understand the reclocking. From looking at the logic I see that the BCK signal from the PCM2706/7 is delayed by one 48MHz clock cycle while the DATA and WS signals are untouched.
The shiftregister reclocker delays BCK by two clock cycles (U5: QB). The introduced BCK delay is only marginal, so there is no need to reclock both DATA and WS as well.

When using TDA1543 / TDA1541A, BCK needs to have low jitter, since BCK determines the exact moment the sample is placed on the DAC output.

The function of the (shiftregister) reclocker is to lock the fluctuating BCK clock signal to the master clock transients. BCK can now only change on the (positive) going edge of the master clock.


Quote:
To me this makes sense to allow the WS and DATA signals to settle out of the jitter zone and BCK is now clocked from the 48MHz clock which has less jitter then from the PCM2706/7
Both DATA and WS are still sampled correctly, the only difference is that BCK jitter, introduced by the PCM2706 PLL / clock recovery circuit, is now removed by "locking" BCK to the low jitter masterclock transients.


Quote:
But I don't understand the relationship between the 48MHz clock and BCK from the PCM2706/7. I wish I knew how the PCM produces BCK from the 12MHz clock. I found the SPACT patent but it is too broad in scope to tell me much
It's logical to use a master clock frequency that's close to a multiple of BCK, but in case of the PCM2706, we also need a 12 MHz clock. Since the PCM2706 PLL is influenced by the 12 MHz clock signal, it's not a bad idea to run both 12 MHz clock and the master clock in sync.

So after some calculating, I ended up with a 48 MHz master clock. When divided by 4, I get the desired 12 MHz clock signal for the PCM2706. The master clock is almost 17 times higher than BCK (48,000,000 / 2,822,400 = 17.0068).


Quote:
If 48MHz was evenly divisible by BCK and synchronous to it then it would make perfect sense to me. But since they don't seem to be then how can they act together to produce a correct reclocked BCK signal without beating or at all?
Well the 48 MHz comes pretty close already (17.0068, deviation: 0.0068)

The custom made oscillators with the WF10192 chip has a specific 16 MHz crystal type that oscillates at a slightly lower frequency than 48 MHz (third overtone), in fact it's very close to 47.98 MHz. This results in a 11.995 MHz clock signal for the PCM2706 (within tolerances), and 47,980,000 / 2,822,400 = 16.9997 (deviation: 0.0003). So now the master clock is almost a perfect multiple of BCK as well. It's even possible to have custom crystals made that are suitable for operation at the third overtone (15.9936 MHz), when multiplied by 3, we get 47.9808 MHz, an exact multiple of BCK.

The "synchronous" part is a bit more difficult, since both BCK and the master clock aren't synced. Here's where the shiftregister reclocker comes-in. The shiftregister reclocker is a combined digital one-schot, and dual-stage asynchronous reclocker. 9 master clock pulses after the rising edge of the BCK input signal, both shiftregisters receive a forced-reset (I needed 2, in order to achieve a delay of 9 master clock pulses). Now the shiftregister reclocker is ready to get a pre-defined lock on the next rising edge of BCK (since it's reset slightly earlier). This mechanism enables BCK to be synced to the master clock.
  Reply With Quote
Old 2nd July 2007, 10:36 PM   #1598
ecdesigns is offline ecdesigns  Netherlands
diyAudio Member
 
Join Date: May 2006
Location: Holland
Default TDA1541A DEM clock frequency / decoupling cap value

Hi onnosr,


Thanks for your reply [post #1596]


Quote:
I tried the dem osc running on 705,6 khz (instead of 352,8)
coupled direct via 470 pf to pin 16 (pin 17 0.2 mf to agn)

soundstage is more massive imho

Pse give it a try and tell us your outcome.

the tda1541a is able to handle that freq.

The TDA1541A active dividers have their limitations (maximum switching speed), pushing these limits could result in increased errors (settling time), and increased power consumption. TDA1541A chips have some tolerances, so one chip could work fine with 705.6 KHz, the other wouldn't.

However, there seems to be a consistent improvement in perceived sound quality with increased DEM clock frequency. So the effect you observed is correct.

The answer is simple, the filter (decoupling caps) produces lower current ripple as the DEM clock frequency increases. So instead of pushing the DEM clock frequency limits, it's also possible to increase decoupling capacitor values.

The DA1541A modules with the new smaller heatsink can accomodate 0.68uF decoupling caps. This is possible by placing half of the caps on the component side, the other half on the solder side (there is plenty of room underneath the modules). The 1 uF for MSB could be increased to 2.2uF if desired.

That should be more than sufficient to get very low ripple current on all active divider outputs.
  Reply With Quote
Old 3rd July 2007, 03:31 AM   #1599
maxlorenz is offline maxlorenz  Chile
diyAudio Member
 
maxlorenz's Avatar
 
Join Date: Oct 2003
Location: osorno , Chile
Hi -ecdesigns-

I confess that I had not see before your excellent and very detailed assembly instructions at your "downloads" page. Wow.

I wait some R to begin with the DI8*4 project. This time I will take my time. Don't expect objectivity from my part with this one

Cheers,
M
  Reply With Quote
Old 4th July 2007, 10:05 AM   #1600
Brent Welke is offline Brent Welke  Canada
diyAudio Member
 
Join Date: Jun 2004
Location: Victoria, BC
Default BCK Reclocking

Hi ecdesigns,

Thank you for answering my questions about your reclocking. I was glad and sad to hear I hadn't missed something simple

What minimum scope spec would you recommend to be able to view BCK jitter like the images you posted? Not that I can run out and buy a new scope, but who knows. Maybe some kind sole will invite me over to use his scope

I have done more A/B testing between reclocking on/off. On the same DAC reclocking always sounds better. Until recently my favorite (burned-in) non reclocked DAC was more pleasant to listen to then the new reclocked DAC. Other then reclocking the DACs are identical in parts.

I would recommend all PCM2706/7 I2S users use/try your reclocker, even those with with super clocks.

To modify my DAC I used SMD parts to make the mod almost invisible. Here is my DigiKey.com parts list for anyone interested in a SMD mod for their existing USB DAC:

568-2619-5-ND IC SYNC 4BIT BINAR COUNTR 16SSOP
296-14020-1-ND IC SHFT REG SERIAL 8BIT 14-TSSOP
NC7SZ04P5XCT-ND IC INVERTER UHS SINGLE SC70-5
CTX315LVCT-ND OSC CLOCK 48.0000 MHZ 3.3V SMD

My camera is out of town for a week or I would post a picture of it.

~~~~~~~~~~~

Point-to-Point SMD building tip -> before you begin rub off all IC pins that are 'No Contact' or bridge them to other pins, which ever works best for that pin position. Buy extra chips. The more you work with SMD parts the easier it becomes. At first you think there is no way you could use such small parts.

~~~~~~~~~~~

USB A/B testing tip -> On a Windows machine using the latest versions of Foobar and ASIO you can send the same audio stream to more then one USB DAC at a time. This makes for very nice A/B testing and to burn-in many DACs from one machine.
  Reply With Quote

Reply


Building the ultimate NOS DAC using TDA1541AHide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off

Forum Jump


New To Site? Need Help?

All times are GMT. The time now is 05:28 AM.


Search Engine Optimisation provided by DragonByte SEO (Pro) - vBulletin Mods & Addons Copyright © 2018 DragonByte Technologies Ltd.
Resources saved on this page: MySQL 15.00%
vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2018 DragonByte Technologies Ltd.
Copyright ©1999-2018 diyAudio
Wiki