Building the ultimate NOS DAC using TDA1541A

Hi maxlorenz,

Dear EC,
Have you tried your own charge transfer supply on your new amps?
I like the way your test amps look like.

No, battery power supply for the SD-player, passive volume control (power switched-off for "audiophile" mode), and mains power supply for the bridge power amps only.

The bridge power amps appear to have high PSRR when fine-tuned correctly, so power supply properties don't have that big effect on performance. There is no ground loop either as the bridge power amps are the only devices connected to the mains (no ground loop).

For the SD-player there is only one option, battery power supply. This also applies for the TDA1543, it will only perform optimally when running on extreme clean power supplies. The specified noise levels for NiMH battery power supplies (that perform best on the SD-player) equals approx. -205dB, this is before filtering.

Talking about DAC chips, based on the resolution "issue", DACs with simplest output stage are likely to provide highest resolution (not bit resolution). Both TDA1541A and TDA1543 have very simple straight-forward output circuits:

Reference current source > (passive) current dividers > bit switches.

Modern DAC chips often contain multiple cascaded buffer / amplifier stages, from a "resolution" point of view this is far from optimal.
 
Isee the grounds & Vbus connected in the diagram for the Adum - hardly galvanic isoaltion, is it? I don't think that the ground can be left disconnected as the D+ & D- are used both differntially & for single ended-signals (so ground is the reference)!

see here: http://www.beyondlogic.org/usbnutshell/usb2.htm

Sorry ecdesigns,
I posted this in the wrong thread - thanks for replying anyway :eek: :)
 
battery bias vs LED

I originally used NiMH battery bias (3.8-4V, with 910R I/V), now switched to LED per EC's new design, battery sounds congested in middle-low range. (not sure if others have same feeling) I was using Silver mica 2200P as bypass.

Anyway, thanks EC again for the great design, LED power supply, LED bias, DJA and Async-reclock do make a huge difference.

Regards
 

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Dear EC,
Thanks for you previous detailed explanations.

No, battery power supply for the SD-player, passive volume control (power switched-off for "audiophile" mode), and mains power supply for the bridge power amps only.

The bridge power amps appear to have high PSRR when fine-tuned correctly, so power supply properties don't have that big effect on performance.

I see, but, didn't you have the curiosity to try the effect of the CT supply on high power circuit???

Who knows where to get short optical cables to do the Toslink isolation mod inside the box?
On second thought, maybe it is better to power both PCm2706 and Toslink emiter from USB bus, as a extension box --> optical cable-> Toslink receiver fed by the DAC's own power supply at the DAC's box. (?)

Regards,
M
 
Hi maxlorenz,

I see, but, didn't you have the curiosity to try the effect of the CT supply on high power circuit???

Yes, but constructing a high wattage (25 ... 120VA) CT power supply could be problematic as it would require very high capacity buffer caps (100,000 ... 470,000uF), and resulting high peak charge currents. This would probably make matters worse. CT power supplies are primarily intended for low power applications.

Who knows where to get short optical cables to do the Toslink isolation mod inside the box?
On second thought, maybe it is better to power both PCm2706 and Toslink emitter from USB bus, as a extension box --> optical cable-> Toslink receiver fed by the DAC's own power supply at the DAC's box. (?)

The question would be what introduces higher jitter levels and or unwanted jitter spectrum, USB or Toslink interlinks?

Based on this, one could either use very short USB or Toslink interlinks. The jitter will end up in the connected DAC anyway, its a no-win situation, with or without jitter blocking due to crosstalk. Theoretically this crosstalk could be fully blocked but in practice it's a different matter.

I performed some tests, and shortest Toslink interlinks appeared to work best, I even constructed a "custom" interlink of approx. 3cm, directly placed between Toslink optical transmitter and Receiver. But it's difficult to polish the side that was cut off. I used sandpaper with fine grit (1200) and plastic polish used to remove scratches on perspex. Finally I turned a small washer that centers the side that was cut off.

Then there is jitter introduced by the PCM2706/7 (on chip PLLs and SpAct).

In order to achieve best performance from the SpAct, it requires both, extreme low jitter reference clock (since it drives an on-chip frequency multiplier that is used tor the SpAct), extreme low noise power supply (to enable best PLL performance). However, there are also integrated headphone amps on the chip that cause significant interference, even when not connected.

Anyway, my suggestion would be using an extreme low jitter 12 MHz clock, and external battery power supply with LED voltage regulator (self powered). This will also prevent unwanted ground loops.

Although not optimal, use the ADUM4160 Full/Low speed USB Digital Isolator and skip Toslink. This way some galvanic insulation is provided and adding additional Toslink induced jitter is prevented. The ADUM160 uses on-chip air coils for data transmission and providing galvanic insulation.

Also make 100% sure the computer and installed software doesn't tamper with the digital audio data, this is rather difficult to avoid and to test.

The Apple AE solution works, but here jitter on the Toslink output is too high. So I would have to crack the housing and redesign the unit in order to improve on this. Latest AE modules use subsequent frequency corrections (bit clock keeps changing stepwise), this can be easily verified with a digital frequency meter. This makes the new AE modules unsuitable for high performance audio.

Oh yes, that's another tiny "issue" with the majority of digital audio sources. They fail to provide exact sample rate frequency, they might provide 44.098 or 44.103 KHz instead of the required 44.100 KHz, this again can be easily verified by a frequency meter. If the playback sample frequency slightly differs from the specified sample frequency, the pitch changes (similar like with a pick-up turntable that turns slightly too slow or to fast). Now try to correct this with a computer-based digital audio source. With a CD transport one could fine adjust master clock frequency, the 3-crystal clock in the SD-player is fine tuned (trimmer) to derive exact 44.100 KHz sample rate. This also means that its desirable to have a tunable OCXO master clock that also offers extreme low jittter.

The I2S signals generated by the PCM2706/7 will still contain considerable jitter (up to approx. 200ps rms), so reclocking is required. Perhaps it's best (and easiest) to use the shift-register reclocker for this. I still have to test this shift-register reclocker with the new 3-crystal clock, perhaps it could perform better then, as performance mainly depends on crystal oscillator intrinsic jitter. I also didn't test the DJA (Dynamic Jitter Attenuation) circuit with this configuration yet.

The setup would then look like this:

USB(computer) > ADUM160 > PCM2706/7 (self-powered by battery and LED regulator, low jitter 12 MHz reference clock) > Shiftregister reclocker (using ultra low jitter clock, exact multiple of fs) > DJA > DAC chip.
 
Oh yes, that's another tiny "issue" with the majority of digital audio sources. They fail to provide exact sample rate frequency, they might provide 44.098 or 44.103 KHz instead of the required 44.100 KHz, this again can be easily verified by a frequency meter. If the playback sample frequency slightly differs from the specified sample frequency, the pitch changes (similar like with a pick-up turntable that turns slightly too slow or to fast). Now try to correct this with a computer-based digital audio source. With a CD transport one could fine adjust master clock frequency, the 3-crystal clock in the SD-player is fine tuned (trimmer) to derive exact 44.100 KHz sample rate. This also means that its desirable to have a tunable OCXO master clock that also offers extreme low jittter.

Great post John, you do give a lot of info on these boards & I thank you for this.
Does it really matter if the clock speed is consistently off by this small fraction - who has such perfect pitch to be able to determine a .005% difference (as long as it doesn't fluctuate)
 
Hi maxlorenz,

The setup would then look like this:

USB(computer) > ADUM160 > PCM2706/7 (self-powered by battery and LED regulator, low jitter 12 MHz reference clock) > Shiftregister reclocker (using ultra low jitter clock, exact multiple of fs) > DJA > DAC chip.

Hi John, do you think Wadia has a good solution for galvanic isolation with the ISO150?
Here is a quote from their site:

"Isolated Digital Coupler Array
The first element in the D>A section is an array of Burr Brown ISO150 Isolated Digital Couplers. These devices are placed between each of the incoming digital signal lines and the DAC chips to provide complete electrical isolation of all signal and ground lines. This prevents any digital noise and ground currents from the digital circuitry from adversely affecting the performance of sensitive analog signals in the 922 D>A section. Some digital products use optically-coupled isolators to isolate the digital inputs. The ISO150 avoids problems commonly associated with optocouplers, as optically isolated couplers require high current pulses and allowance must be made for LED aging. Optical isolators can exhibit a 50% reduction in light output from their internal LED within one year. In a worst-case scenario, this degradation could cause a performance or reliability issue. Since the ISO150 uses no LEDs, aging is not a factor and reliability and lifespan are greatly increased. The ISO 150 devices used in the 922 Decoding Module utilize a tiny internal air gap that acts as a capacitor by transferring high frequency signals. These devices allow data up to 80 Mbits/sec to be transmitted, while still achieving a very high degree of DC and low frequency isolation. Although the air gap is small, each device can withstand peak voltages up to 2400 volts."

Based on the performance of most of their previous Gear their approach with
the ISO150 should be a step forward.

Klaus
 
Thanks for your reply, EC. (post#3026)

I have used CT supply on several amps: 5W classA; 38W class AB; 100W classD. All with 20.000 to 23.300uF per PS polarity. Though I plan to increase capacitance as funds allow, the sonics are stunning so no urge to do it (plus there is the fact that space restrictions are limiting).

Maybe I'll try both USB isolation ways and compare. ;)

Dear John, I have to abuse of your kindness again:
I am still having trouble to connect CD PRO's I2S to the D1M as DATA signal seems too small. A DIY upscalling transformer did not work. I will try with an attenuator circuit with variable R just to see if I get something. IF not, could I use Fairchild 125 UHS buffers to pass BCK, WS and DATA or will it add too much jitter or be too slow???

Thanks,
M
 
Cd Pro .....

I am still having trouble to connect CD PRO's I2S to the D1M as DATA signal seems too small. A DIY upscalling transformer did not work. I will try with an attenuator circuit with variable R just to see if I get something. IF not, could I use Fairchild 125 UHS buffers to pass BCK, WS and DATA or will it add too much jitter or be too slow???

I am using I2S from a Cd Pro2 to my 4x TDA1541 DAC. It uses a 74HC157 to mux between the on board DIR9001 and the I2S input. The 157 feeds a 26LS31 line driver that feeds the 4 DACs with damping resistors to each.

This seems to work great with Cd Pro. I have a total of about 16" of wire connecting the Cd Pro I2S output to the 74HC157 MUX.

I use very good & short TOS cable to a TOS receiver going direct to the DIR9001. I bypassed all the Cd Pro on board SPDIF electronics ahd connected a TOS driver to the control chips SPDIF output... I can hear a small but noticeable improvement of the fine detailing when switching to I2S from the TOS.

I also reclocked the Cd-Pro to a .5ppm clock, that is a must do in my opinion and maybe I will try an even better clock ....I immediately heard the improvement with .5 ppm. The stock clock on Cd Pro does not seem to be very good.

The Cd-Pro puts out a 48 bit I2S word by default. In emailing John and mentioned in this thread many posts back, the DI-8 expects 64 bit I2S.

There is a command for the Cd-Pro to change the word length, but my Transport kit does not provide access to those commands via the Cd-Pro control port. I contacted the provider of the transport kit...no control command. So I have never tried to change the word length to see if it works.

Some Cd-Pro transport kits provide a means to change the Cd-Pro configuration via the front panel control buttons...not mine. This winter I build a 48 bit version of John's delay circuit, so that I can run I2S.

What word length are you using?

johnk
 
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Hi JohnK,
Thans for your input.
Today I successfuly connected CDPRO to D1M (48FS): the attenuator worked OK when I dimished DC to 1.23V on DATA stream. I did not had the time to adjust WS nor to apply dinamic jitter attenuator to BCK. Instead of replacing the transport's clock, which may be difficult and risky, I would prefer to reclock externally the BCK.

Cheers,
M
 
Hi jstang,

The Cd-Pro puts out a 48 bit I2S word by default. In emailing John and mentioned in this thread many posts back, the DI-8 expects 64 bit I2S.

It's possible to change the timing module:

Current configuration contains delays with multiples of 16 (DI4), or 8 (DI8) and was designed to support 64 bits / frame only.

All you have to do to get 48 bits / frame from the CDPRO II working is using delays with multiples of 12 (DI4) or 6 (DI8) instead.

Easiest way to achieve this is using 74HC164 shift registers that have 8 outputs. By cascading these, one can put taps at desired locations: 1, 2, 3 … 64.

In order to have all DAC chips latch simultaneously, use a delay for the first DAC chip too. Example for DI4, 48 bits / frame:

SN74HC164 #1, output 1 > DAC chip #1 (1 BCK delay).
SN74HC164 #2, output 5 > DAC chip #3 (13 BCK delay).
SN74HC164 #3, no outputs connected to DAC chips.
SN74HC164 #4, output 1 > DAC chip #2 (25 BCK delay).
SN74HC164 #5, output 5 > DAC chop #4 (37 BCK delay).

DATA outputs with 25 and 37 BCK delay can be inverted for balanced output configuration.

Output 8 of each 74164 connects to both data inputs of the following 74HC164 chip. All clock inputs are connected in parallel and connect to BCK. All DAC chips are clocked with inverted BCK.

This solution requires 5 x SN74HC164 for DATA, and 5 x SN74HC164 for WS, and some buffers / inverters.

I could post schematics of a 48 bits / frame interpolator for DI4 and DI8.
 
Dear JohnK,
Sixteen inches seems too long for I2S...are they in separate boxes?

Separate boxes directly on top of each other.... The length might be less...I am going from memory and I am not at home. But the 16" ( or less inches ) is from CD-Pro PC board to DAC PC board.... Inclusive of internal wiring and a short 4" external jumper.

Hey John,

If you get a chance to post the 48 bit schematic....please do, greatly appreciate your sharing!!! I was thinking the same number of shift registers.


jk
 
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Hi maxlorenz,

Instead of replacing the transport's clock, which may be difficult and risky, I would prefer to reclock externally the BCK.

It's best to use a single masterclock for both CDPRO II and connected DAC, otherwise reclocking will be asynchronous and you still end up with a lot of interference (jitter) from the poor quality on-board SMD crystal oscillator.

Here is how to perform the modification with minimum risk of damaging the 4-layer PCB:

http://www.diy-high-end.com/index_bestanden/Page2334.htm


External masterclock frequency equals 8.4672 MHz, you can buy suitable low jitter clock from TentLabs:

http://www.tentlabs.com/Products/cdupgrade/xo2xo3/index.html

Don't forget to connect it to an extreme low noise filtered and stabilized (LED voltage regulator) battery power supply.

Next synchronously reclock WS, DATA and BCK using separate high-speed D flip-flops:

DATA > D input flip-flop > Q output connects to DATA input of DAC chip, clock input connects to inverted masterclock.
WS > D input flip-flop > Q output connects to WS input of DAC chip, clock input connects to inverted masterclock.
BCK > D input flip-flop > Q output connects to BCK input of DAC chip, clock input connects to inverted masterclock.

Power supply for the D flip-flops must be just as clean as the crystal oscillator power supply, also use a separate voltage regulator and filter for each D flip-flop.


Hi jstang,

12" (30cm) is way too long for I2S. For maintaining low jitter, use shortest possible I2S interlinks, more like 1.2" 3cm maximum, especially for BCK.

Also make sure there is absolutely no crosstalk between both DATA and BCK lines as this results in very high jitter.

Use either suitable screened wires or increase distance between both BCK and DATA / WS wires.
 
On the I2S length with CD-Pro, I have seen several different kit implementations that the length is 12" or even more... Mine is shorter than the typical I2S implementations in most kits.

Not saying that is ideal.

But I would like to find a schematic of the CD-Pro2 board to see what they are using to drive the I2S output. Fundamentally, all I2S connections will be off board for the CD-Pro and will always be used via a cable. So I am wondering if Philips provided for that requirement.

jk
 
Thanks EC for your excellent reply about I2S reclocking of CDPRO and DAC. (post # #3036).
Would you care to mention suitable high speed D flip-flop...that would be on Digikey's catalog? :goodbad:

This is a nice project to challenge my limited skills. According to how the player is sounding with the test set-up, it surely has some potential,. :cool:
...I hope some charitable soul would come up with a schematic...:D
 
Next synchronously reclock WS, DATA and BCK using separate high-speed D flip-flops:

DATA > D input flip-flop > Q output connects to DATA input of DAC chip, clock input connects to inverted masterclock.
WS > D input flip-flop > Q output connects to WS input of DAC chip, clock input connects to inverted masterclock.
BCK > D input flip-flop > Q output connects to BCK input of DAC chip, clock input connects to inverted masterclock.
Hi EC,
Why is it necessary to reclock the DATA and WS signals? Reclocking BCK wouldn't be enough?
 
Would you care to mention suitable high speed D flip-flop...that would be on Digikey's catalog?

I guess I can use 74HC164 (or HCT) shiftregisters as D flipflops, one for each signal--> DATA, WS and BCK goes to A+B inputs; CLR goes high, output is taken from QA and CLK gets the new master clock at 8,4MHz, right?
The inverted Clock puzzles me, though...

Thanks,
M