Hi there,
I'm developing an FPGA-based DSP sound processing platform.
I am planning to do this as an OEM PCB board.
Short brief about the DSP processing platform.
1. Total number of channels processing - 128.
2. Processing path - 64 bit float point (IEEE 754 double precision).
3. Sampling rate - 96 kHz.
4. Latency processing - about 200 microsecond (20 tick 96 kHz sampling rate).
5. Input channels - 128 with digital trim, polarity, LPF/HPF filters, 8-band parametric EQ, compressor, gate and limiter section (maybe in future - multi-band), channel gain and panorama.
6. Mixing matrix - 128x128 with gain crosspoint.
7. Output channels - 128 with 8-band parametric EQ, 32-band graphic EQ, compressor, gate and limiter section.
8. Input/Output interface - master multichannel I2S (16 input / 16 output line (8 channels in each line), 24.576 mHz bit clock, common bit clock and frame sync signals).
It's possible to change the internal architecture during the development process.
I hope this project will be interesting for someone. Also I would like to hear anythings from interested people.
I'm developing an FPGA-based DSP sound processing platform.
I am planning to do this as an OEM PCB board.
Short brief about the DSP processing platform.
1. Total number of channels processing - 128.
2. Processing path - 64 bit float point (IEEE 754 double precision).
3. Sampling rate - 96 kHz.
4. Latency processing - about 200 microsecond (20 tick 96 kHz sampling rate).
5. Input channels - 128 with digital trim, polarity, LPF/HPF filters, 8-band parametric EQ, compressor, gate and limiter section (maybe in future - multi-band), channel gain and panorama.
6. Mixing matrix - 128x128 with gain crosspoint.
7. Output channels - 128 with 8-band parametric EQ, 32-band graphic EQ, compressor, gate and limiter section.
8. Input/Output interface - master multichannel I2S (16 input / 16 output line (8 channels in each line), 24.576 mHz bit clock, common bit clock and frame sync signals).
It's possible to change the internal architecture during the development process.
I hope this project will be interesting for someone. Also I would like to hear anythings from interested people.
Last edited:
Sounds great, are you planning to make it a free form DSP like Symetrix, QSC etc.? or fixed processing flow?
I would recommend doing ASRC on all digital inputs, many limitations from having to be I2S master.
You don't have to use 64bit floating point, 40 bit is sufficient for 24bit audio.
What FPGA are you using?
I would recommend doing ASRC on all digital inputs, many limitations from having to be I2S master.
You don't have to use 64bit floating point, 40 bit is sufficient for 24bit audio.
What FPGA are you using?
Member
Joined 2018
Kintex 7 is good, relatively easy to use (I find using one of the Xilinx FPGAs with a built in CPU involves a lot more setup). You don't have to use the system builder in Vivado with the Kintex. If you haven't used Vivado before one thing to be aware of is that projects have poor portability between Vivado versions.
You should also consider dynamics processing blocks, dynamic EQ, compressor and limiters. As Cyber pit says monitoring is also important, I would add peak hold on the level meter and some sort of fft would be cool.
You should also consider dynamics processing blocks, dynamic EQ, compressor and limiters. As Cyber pit says monitoring is also important, I would add peak hold on the level meter and some sort of fft would be cool.
A Pi4 can do quite a lot today...
https://www.diyaudio.com/forums/pc-...crossovers-correction-etc-66.html#post6637817
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https://www.diyaudio.com/forums/pc-...crossovers-correction-etc-66.html#post6637817
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