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i/v stage problem
i/v stage problem
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Old 14th March 2021, 01:12 PM   #1
maxpou is offline maxpou  Canada
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Default i/v stage problem

Hi,
i built this stage iv for the PCM1798 or COD from twisted pear audio, but i don't understand why i have dc offset at the output ( 0.7V) while my j-fets are match paired. I have this problem when I put a cap in C7 and C8.

Someone can help me?

Thank you! Maxpou
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Last edited by maxpou; 14th March 2021 at 02:50 PM.
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Old 14th March 2021, 01:26 PM   #2
Ken Newton is offline Ken Newton  United States
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So, when C7 and C8 are removed there is no D.C. offset?

If yes, then measure the D.C. voltage at the drain of Q4 and the gate of Q5, with C7 and C8 in place, to see if they are symmetrical with respect to ground. If there's an imbalance, my first guess is that one of those 1,000uF e-lytic caps may be leaking D.C. Obviously, the offset should not be affected by C7/C8 which should function as open circuits at D.C.

Last edited by Ken Newton; 14th March 2021 at 01:52 PM.
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Old 14th March 2021, 01:45 PM   #3
Lampie519 is offline Lampie519  Netherlands
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Maybe the FET's are matched but not your resistors (4.7 Ohm). Only a slight mismatch could give this DC offset.
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Old 14th March 2021, 01:49 PM   #4
maxpou is offline maxpou  Canada
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Hi Ken,
thank's for reply. my first test was to change the capacitors for 100uF, without success, 2nd I lowered the resistors R8 and R9 by half, without success and my last test was to change my j-fets without success too.

Maxpou

Last edited by maxpou; 14th March 2021 at 01:54 PM.
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Old 14th March 2021, 01:53 PM   #5
maxpou is offline maxpou  Canada
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Quote:
Originally Posted by Lampie519 View Post
Maybe the FET's are matched but not your resistors (4.7 Ohm). Only a slight mismatch could give this DC offset.
Hi Lampie,
i use the prp resistor 1% and i verified each of them.

Maxpou
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Old 14th March 2021, 01:55 PM   #6
Ken Newton is offline Ken Newton  United States
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Quote:
Originally Posted by maxpou View Post
Hi Ken,
thank's for reply. my first test was to change the capacitors for 100uF, without success, 2nd I lowered the resistors R8 and R9 by half, without success and my last test was to change my j-fets without success too.

Maxpou
1) Just to confirm, there is no D.C. offset with C7/C8 removed?
2) Also, what are the supply voltage readings at the drain of Q4 and the gate of Q5 with and without C7/C8?

Last edited by Ken Newton; 14th March 2021 at 01:57 PM.
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Old 14th March 2021, 01:56 PM   #7
lcsaszar is offline lcsaszar  Hungary
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R7 does not have any effect at all?
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Old 14th March 2021, 03:03 PM   #8
maxpou is offline maxpou  Canada
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Quote:
Originally Posted by Ken Newton View Post
1) Just to confirm, there is no D.C. offset with C7/C8 removed?
2) Also, what are the supply voltage readings at the drain of Q4 and the gate of Q5 with and without C7/C8?
Hi Ken,
no d.c. offset without C7/C8 and i have 10.15V in drain of Q4 and 10.26V in gate of Q5.

Thank's Maxpou
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Old 14th March 2021, 03:05 PM   #9
maxpou is offline maxpou  Canada
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Quote:
Originally Posted by lcsaszar View Post
R7 does not have any effect at all?
Hi,
no because i have a coupling cap C2.

Maxpou
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Old 14th March 2021, 03:27 PM   #10
Lampie519 is offline Lampie519  Netherlands
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Try to put a potmeter of 100 ohm with 10 ohm in series over R6 and check if you can adjust to 0v on the output.

Last edited by Lampie519; 14th March 2021 at 03:31 PM.
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