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The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker
The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker
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Old 14th January 2020, 05:32 PM   #1
andrea_mori is online now andrea_mori  Italy
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Default The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker

Since the latch signal is crucial to get the best performance from a DAC we are developing a FIFO re-clocker that runs slave to the master clock.

In other words the FIFO buffer and re-clocker FPGA based does not manage the latch of the DAC (WS signal in I2S format and LLLR in PCM format) that comes directly from the master clock via a programmable divider isolated from the other digital circuits.
This to avoid any interference between the FPGA based digital circuit and the conversion circuit inside the DAC.

Every time the latch signal switches new data are asked to the FPGA, using all optical isolated lines.
This is a different approach in respect to other similar devices where the FPGA works on all I2S signals including the word select.

There will be 3 boards, the main FIFO re-clocker and the optional User Interface and Output Interface boards.

The main board has 4 I2S input selectable by the User Interface board.
Also the dithering process is selectable via the User Interface board.

There are 2 output options, both with header and u.fl connectors.
The main board needs 2 master clock signals, one for each sample rate family.
It can accommodate the Crystek or NDK oscillators, but a pair of very low phase noise are strongly suggested (5.6448 MHz up to 24.576 MHz).

More infos next days, a prototype is on the way.
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File Type: jpg TWSAFB-OI.jpg (123.1 KB, 1572 views)
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Old 14th January 2020, 09:41 PM   #2
pinnocchio is offline pinnocchio  Canada
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That’s very nice work!
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Old 15th January 2020, 03:35 AM   #3
canvas is offline canvas  Taiwan
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Excellent. This is exactly what I am looking for. I'm in.
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Old 15th January 2020, 03:38 AM   #4
tubo is offline tubo  Philippines
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Greatly interested
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Old 15th January 2020, 12:32 PM   #5
andrea_mori is online now andrea_mori  Italy
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There are several output types available: I2S fixed length (32 bit), I2S variable length (selectable data length) and PCM.
The output formats available are: Two's complement, Offset binary (TDA1541A) and a custom format (sign magnitude + first 3 MSBs thermometer decoded) to be used with our new discrete DAC.

The data length is selectable from 16 up to 32 bit.
The bit clock mode is selectable between stopped clock adn continuous clock.
It accepts sample rate from 44.1 up to 384kHz.

The FPGA digital circuit is totally isolated from the master clock section using high speed optocouplers.
The master clock selection between the two sample rate families is performed using relŤ instead of digital multiplexer.
We have took the maximum care to avoid any RF interference between the FPGA section and the clock section.

The master clock section uses a separate power supply (3V3), we suggest battery power supply. We are developing a LiFePo4 power supply system, it will be available next months.
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Old 15th January 2020, 01:12 PM   #6
canvas is offline canvas  Taiwan
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Andrea,

I don't like digital multiplexer, too. However, the relay can be problematic due to impedance mismatch and coil interference. BTW, it is possible to reclock critical signal (i.e. LE, BCK) with independent flip-flops? I'm afraid octal flip-flops tend to interfere with each other inside the package.
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Old 15th January 2020, 02:05 PM   #7
ilgavro is offline ilgavro
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I follow threads
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Old 15th January 2020, 05:15 PM   #8
andrea_mori is online now andrea_mori  Italy
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Quote:
Originally Posted by canvas View Post
Andrea,

I don't like digital multiplexer, too. However, the relay can be problematic due to impedance mismatch and coil interference. BTW, it is possible to reclock critical signal (i.e. LE, BCK) with independent flip-flops? I'm afraid octal flip-flops tend to interfere with each other inside the package.
There is no coil interference since double coils latching relays have been used. LE
Is reclocked at output with master clock. BCK is not a crucial signal and so it is optically isolated from the master oscillators and not reclocked.
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Old 15th January 2020, 06:16 PM   #9
diyiggy is offline diyiggy
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Excellent Andrea,
thank you for that, count me in.
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Old 15th January 2020, 08:27 PM   #10
gabor80 is offline gabor80  Hungary
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Andrea,
Is it similar to Iancanada FIFO reclock? Or it will better performance?
What is the min. divider, can it use 6 MHz clock for 96 or 192KHz sample rate?
Thanks, and good job!
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