The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker

Well, if its isolated via opto and distanced by a few meter, I cant see how that is possible. Please provide a technical explanation - I'm curious.

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Not sure where and how many those "few meter" need to be. IME as long as the ethernet cables pass through the music room, everything terminating them becomes audible. And of course, the cables themselves. Optical will solve this particular issue completely.

I just don't see how the fifo is related to any of this.
 
Since the FIFO operates in a different domain nothing should pass from the source, but without proper isolation the FIFO become source dependent.

The FPGA is not the best place to generate the crucial signals to feed the DAC, it adds a lot of jitter as I have already demonstrated.
A very good master clock is the best starting point to generate directly the crucial signal for the DAC, avoiding to cross the FPGA.

Moreover ethernet is not mandatory, I would avoid all RF interferences (Lan, WiFi, BT, remote controls, smartphone and so on) in the listening room. To enjoy these toys I would use another room.
They have nothing to do with hi-end audio.
That's the reason I'm designing a standalone source, obviously in a separate box and far from the digital to analog conversion.
 
I believe both have poor digital output, so the GPIO I2S save me to use one more converter (USB to I2S) since I can connect the I2S output directly to the FIFO.

As I have already said I don't care much about the quality of the I2S output, a true FIFO buffer well isolated is not affected by the quality of the signal coming from the source.
 

TNT

Member
Joined 2003
Paid Member
Not sure where and how many those "few meter" need to be. IME as long as the ethernet cables pass through the music room, everything terminating them becomes audible. And of course, the cables themselves. Optical will solve this particular issue completely.

I just don't see how the fifo is related to any of this.

Is it data integrity or jitter that is your consern? You do of course know that one the dta has been written into a memory, any trace of previous jitter on the incoming line is gone. Remains data intehrity - bit errors, really?!!

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Hi Andrea!
I am very excited about your new range of devices. I believe these are the SOTA of digital reclocking.:):):)
I pretend to use your I2S reclocker (and Driscolls) to build my v3 spdif digital transport to feed my TDA1541 DAC (v3.1 Abbas audio) but I have one doubt. If I connect and I2S-to-SPDIF board to your I2S reclocker, the I2S should be Master and the SPdif out should always work in slave mode. Is it correct?
 
Hi, sorry I didn't explain myself well...I want to build an spdif transport based on your reclocker to feed my spdif input dac. So my question was about adding an i2s to spdif board (abbas hopefully as well) to your i2s reclocker.
In this case the output board should run slave to your reclocker?
 
It looks like that the Mutec is already a reclocker with word clock output and it doesn't provide connection for esternal clock (I believe it use a 10 MHz master clock and a PLL to generate the output frequencies).

Maybe I'm wrong, but I don't think you can reclock the Mutec, because the new FIFO buffer accepts I2S only and its output is I2S/PCM, S/PDIF is not provided as the input and neither as the output.
 
My transport consists of two pcs connected via ethernet. These two PCs can run in a dual software environment, hqplayer (ubuntu) and JPLAY (w2k19 server core). First PC acts as an upsampler for hqplayer embedded or control PC for JPLAY, and the second one is naa for hqplayer or audio PC for JPLAY. Mutec is connected via a heavily modded USB connection to the audioPC/naa (battery and linear ATX powered).


I have not moved to rasp and so on because I want to keep this dual software setup because the last version (v7) of JPLAY sounds really good, and arm devices cannot run windows.

IME I have realized that the better the power and the better the clocks used in the digital chain the better it sounds from a hardware point of view. Then I came across your new line of products which fits perfectly in my conception so I have decided to take a chance.


My first problem is that it does not seem to exist a device that can run both windows and linux and provide an I2S connection (Up2/Xtreme boards seem to be close) to feed your reclocker so I need an intermidiate conversion from USB to I2S (JLSounds) or USB-SPDIF-I2S (Mutec MC3+AK4118 board). Once the I2S stream is in your I2S reclocker the output is conneted to a new board I2S-to-SPDIF into my DAC. I have asked Mr. Abbas to build this new SPDIF board with I2S input and he is considering it at the moment.
I will compare this setup to a raspberry directly into your I2S reclocker anyway.


My first question was about the specs that this new I2S-Spdif board should be compliant (slave/master) to your reclocker. I understand that it should be slave to the reclocker.

Mutec MC3+ USB is a fantastic device actually. It is a digital spdif reclocker and a usb-spdif converter at the same time, and it sounds really good!. Internal USB board is synchronized to a 1Ghz (yes 1Ghz!) clock and reclocking board runs synchronized to a 10Mhz internal clock. It also can be used with an external 10Mhz clock. In fact Mutec has developed a new (audiophile line ;)) external 10Mhz clock, the REF10 SE120 (MUTEC - Professional A/V and High-End Equipment - REF10 SE120), and it seems to be very good, -120dBc/Hz at 1Hz and 15fs from 1-100Hz but it goes to 5k USD/EUR.
 
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TNT

Member
Joined 2003
Paid Member
For i2s you might have a choice of which unit on either side of the bus (cable) that should be slave or master. For s/pdif you don't have this choice - it's always the downstream unit that is slave - thats how this interface works.

The challenge will be to find/build a converter that preserves the phase noise performance of these clocks...

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My transport consists of two pcs connected via ethernet. These two PCs can run in a dual software environment, hqplayer (ubuntu) and JPLAY (w2k19 server core). First PC acts as an upsampler for hqplayer embedded or control PC for JPLAY, and the second one is naa for hqplayer or audio PC for JPLAY. Mutec is connected via a heavily modded USB connection to the audioPC/naa (battery and linear ATX powered).


I have not moved to rasp and so on because I want to keep this dual software setup because the last version (v7) of JPLAY sounds really good, and arm devices cannot run windows.

IME I have realized that the better the power and the better the clocks used in the digital chain the better it sounds from a hardware point of view. Then I came across your new line of products which fits perfectly in my conception so I have decided to take a chance.


My first problem is that it does not seem to exist a device that can run both windows and linux and provide an I2S connection (Up2/Xtreme boards seem to be close) to feed your reclocker so I need an intermidiate conversion from USB to I2S (JLSounds) or USB-SPDIF-I2S (Mutec MC3+AK4118 board). Once the I2S stream is in your I2S reclocker the output is conneted to a new board I2S-to-SPDIF into my DAC. I have asked Mr. Abbas to build this new SPDIF board with I2S input and he is considering it at the moment.
I will compare this setup to a raspberry directly into your I2S reclocker anyway.


My first question was about the specs that this new I2S-Spdif board should be compliant (slave/master) to your reclocker. I understand that it should be slave to the reclocker.

Mutec MC3+ USB is a fantastic device actually. It is a digital spdif reclocker and a usb-spdif converter at the same time, and it sounds really good!. Internal USB board is synchronized to a 1Ghz (yes 1Ghz!) clock and reclocking board runs synchronized to a 10Mhz internal clock. It also can be used with an external 10Mhz clock. In fact Mutec has developed a new (audiophile line ;)) external 10Mhz clock, the REF10 SE120 (MUTEC - Professional A/V and High-End Equipment - REF10 SE120), and it seems to be very good, -120dBc/Hz at 1Hz and 15fs from 1-100Hz but it goes to 5k USD/EUR.

As TNT said when you finally convert from I2S to S/PDIF it's very difficult to preserve the phase noise performance of the clock, tipically S/PDIF is charge of jitter.

IMHO the best way could be if Mr. Abbas provided I2S input for the DAC, this way you preserve the clock performance.

Anyway our FIFO is slaved to the LRCK coming directly froma the master clock, it does not cross the FPGA to avoid interference from the source/FIFO.
This way is the best for the TDA1541A because the crucial signal (the LRCK) is fed directly from the master clock divided down to the required frequency.
 
You both are right, in this case the last spdif board performance is key to overall result....
When I ordered the DAC (upgraded v3.1 with D3A output stage) I asked to implement an I2S input but Mr. Abbas rejected to do so. I would be absolutely fantastic! It is only abailable with spdif input, CS8414 based.
I do not dare to modify the DAC by myself:(:(, do you think that it would be possible? My DAC is this DAC abbasaudio 3.0 2.0 1.0 • (top of the page) without some capacitor and components upgrade that I asked, power supply is also upgraded.....
 
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Yes, it's possible.

Firstly you should measure the voltage at pin 27 with a DMM to understand the mode select configuration.

Then you should remove the CS8414 and feed directly the TDA1541A by I2S or PCM simultaneous depending on the actual mode select configuration.

The TDA I2S pins are 1,2,3 and 1,2,3,4 in simultaneous mode.
I see 3 jumpers on the PCB (R9, R10, R11), maybe they are connected to the I2S input of the TDA, you should look at the bottom of the PCB to understand where they are connected. If they are connected to the I2S input of the TDA1541A (pins 1,2,2) you should simply cut the jumpers and connect the incoming I2S signals to the right side of the jumper.
 
Hi Andrea,

Would you please advise about using your device In PCM63 SM5842 CS8412 based dac
I put main FiFo board with optional output board between SM5842 and PCM63?

There are 2 time domains, so this device works in asynchronous mode. The incoming I2S data are stored in a memory buffer, then there are a pair of external oscillators that provide the master clock. Via a programmable divider the master clock is divided down to get the Latch Enable to feed directly the DAC (the latch signal does not cross the FPGA. The output data from the FPGA are synchronized to the LE, in other words at the rising edge of the latch enable the FPGA provides a new word of data. There is no interaction between Fpga/Mcu and master clock/dividers section (that are optically isolated). There is an optional board to optically isolate bit clock and data coming out from the FPGA and the DAC input.