The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker

[andrea_mori]

Thanks, I’ll do that then!
Quick follow up: I guess that means that even if it is possible to use both i2s outputs at the same time, say one output for my left and one for my right side, probably wouldn’t bring any more benefits than good impedance matching (jitter/performance wise)

Yes, I think so, better if you design a good impedance controlled distribution board fed by a single I2S line. And take care of reflection issue, so cables as short as possible, maybe some low value resistors (eg. 22R) close to the FIFO output.

 

[exclusive]

Hi Andrea,

have you considered pumping out data from the FPGA via SPI to some of the industrial DAC's like AD5791 in sync with the latch. SPI data can be send in a bursts at up to 35Mhz and let say 384k latch.

Great work by the way. Very similar to what we do.

 

[andrea_mori]

Hi Andrea,

have you considered pumping out data from the FPGA via SPI to some of the industrial DAC's like AD5791 in sync with the latch. SPI data can be send in a bursts at up to 35Mhz and let say 384k latch.

Great work by the way. Very similar to what we do.

Not just the way I prefer, but nice idea for those who wants implement such these DACs. I believe we can include this update in a new release.

 

[Hifoli]

Hi Andrea,

I think I remember you said somewhere that the Fifo board will be able to be powered by a multiple of 3,3V for lifepo4 power. I was wondering if the battery powered psu you are currently designing will be able to supply the fifo board + a set of two of your new clocks with power continuously like you recommended (as to speak, the clocks will still be powered in some way while the batteries are charging)?

Greetings Oli

Edit: Just found the answer for the first part, the fifo needs only "clean" power on the 3v3 for the clock section not the 7V(?) input for the FPGA etc., right?

 

[andrea_mori]

The new battery system will provide supply to a pair of oscillators, to the master clock/dividers section of the FIFO, to the DAC.

The PSU board of the battery system will provide linear power supply to the oscillators when battery are disconnected and charging, to the FPGA section of the FIFO.

 

[Hifoli]

Ahh so really all I could wish for, thanks

 

[sumilux]

Wonderful work. Thank you

 

[janho12345]

Andrea, how far are you yet with this thing? (and the dac ? ====)

 

[andrea_mori]

The new FIFO buffer is ready for test.
The Lite version of the DAC is almost ready, we have to test it with the new FIFO buffer because the DAC uses a custom protocol, a sort of segmented PCM.
This is mandatory because the FIFO is slaved to the DAC.
So expect a pair of months.

 

[TNT]

Some more info information on architecture please

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[andrea_mori]

The FIFO buffer architecture was already explained in post #1.

The new DAC Lite is a segmented 16/24 bit 192kHz device.
First 3 MSB are thermometer decoded, the remain are R2R decoded.
It uses sign magnitude notation with a custom protocol.
Data and BCK are optical isolated from the source.

 

[TNT]

Why not a continuous sign-magnitude DAC through all the bits?

Is it really wise to change method up through the bits?

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[andrea_mori]

Thermometer decoding is far superior because only a resistor switches at a time, but needs 2^n - 1 resistors where n is the number of bit of the ladder.

A 24 bit ladder DAC fully thermometer decoded needs 16777215 resistors, that's impracticable, so the thermometer decoding will be limited at the first 3 MSB in the Lite version and at the first 5 MSB in the Top version.

 

[andrea_mori]

To clarify better, let examin a 3 bit ladder DAC as example.

Thermometer/Dec/Switch at 1 time
0000000 0 -
0000001 1 1
0000011 2 1
0000111 3 1
0001111 4 1
0011111 5 1
0111111 6 1
1111111 7 1
always 1 resistor at 1 time

R2R/Dec/Switch at 1 time
000 0 -
001 1 1
010 2 2
011 3 1
100 4 3
101 5 1
110 6 2
111 7 1
4 times 1 resistor at 1 time
2 times 2 resistors at 1 time
1 time 3 resistors at 1 time

 

[nautibuoy]

I'm following this with interest, excellent work that looks to be close to coming to fruition.

Is there more information about this?

The new DAC Lite is a segmented 16/24 bit 192kHz device.

 

[andrea_mori]

-16/24 bit option
- 44.1 kHz to 192kHz sample rate
- segmented architecture, first 3 MSB are thermometer decoded, the remaining bit are R2R
- sign magnitude notation
- voltage output (2Vrms)
- optically isolated BCK and DATA to avoid any interference from the source
- stopped clock option
- custom PCM segmented protocol (implemented in the new FIFO buffer)

 

[nautibuoy]

Thanks. Is this on paper or being physically realised as a prototype - I looked to see if there was another thread on it but perhaps it is integral to the Fifo project.

 

[andrea_mori]

The first prototype is ready to be tested with the new FIFO buffer.

Expect at least 1 month for the test, after I will start a dedicated thread.

 

[nautibuoy]

 

[TNT]

Whatif the segments sound "differently"?

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