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The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker
The Well synchronized asynchronous FIFO buffer - Slaved I2S reclocker
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Old 15th January 2020, 09:51 PM   #11
andrea_mori is offline andrea_mori  Italy
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Quote:
Originally Posted by gabor80 View Post
Andrea,
Is it similar to Iancanada FIFO reclock? Or it will better performance?
What is the min. divider, can it use 6 MHz clock for 96 or 192KHz sample rate?
Thanks, and good job!
192 khz pcm and 96 khz i2s
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Old 17th January 2020, 12:02 AM   #12
canvas is offline canvas  Taiwan
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I see some regulators on board. Will you consider better ones like LT3045? Or, just add an external power connector.
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Old 17th January 2020, 01:26 AM   #13
andrea_mori is offline andrea_mori  Italy
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Quote:
Originally Posted by canvas View Post
I see some regulators on board. Will you consider better ones like LT3045? Or, just add an external power connector.
LDO on board are just to power FPGA and MCU, so there is no reason to use better ones. Only for master clock and divider a very good power supply is needed, battery suggested.
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Old 19th January 2020, 07:36 PM   #14
Zoran is offline Zoran  Serbia
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Good news Andrea.
I am waiting for D-day...
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Old 20th January 2020, 08:11 PM   #15
Raj1 is offline Raj1  United Kingdom
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Interested.
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