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AK4499 DAC Design
AK4499 DAC Design
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Old 6th December 2019, 07:17 PM   #131
adam1016 is offline adam1016  United States
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Yes, you make a good point, at this stage however I would like to keep the design as modular and open as possible, I have some ideas on how to keep the FB loop shorter than the Buffalo Style. I'm also not building this for commercial purposes yet, would just like a dac experiementation test bed that can be shared and iterated upon openly by the community.
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Old 6th December 2019, 09:26 PM   #132
samoloko is offline samoloko  Bulgaria
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where that came from

Quote:
Originally Posted by Markw4 View Post
Somoloko,
The output pins with the same signal names are supposed to be paralleled as has been done by Adam.
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Old 6th December 2019, 10:29 PM   #133
Markw4 is offline Markw4  United States
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Quote:
Originally Posted by samoloko View Post
where that came from
The AK4499 data sheet lists all the pins, for example one entry in the table says:

Pins____Name________Discription
83,84__ IOUTL2P__O__ Current Output pin (L2ch positive signal).

The column with a capital O in it indicates the signal is an output.

In other words, the exact same signal is on two pins, probably in order to help keep output impedance very low.

Also, the schematics for the AK4499 eval board show the pins connected in parallel.

Nothing is lost by doing that since from the description you can see they are both the same signal: Left-side, Channel-2, Positive output (positive phase, if you want to use that term). There are another two pins for the negative signal (or negative phase). No information is lost. Each unique output signal passes through its own I/V stage then goes all the way to the differential output XLR connector for that channel.

Hopefully that makes sense. If not, please let us know.
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Old 7th December 2019, 12:47 AM   #134
redjr is offline redjr  United States
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AK4499 DAC Design
Quote:
Originally Posted by John Luckins View Post
+1

I agree wholeheartedly with Marks input to this thread with respect to power supplies based on my experience with many different regulator types on other DACs. It would be nice if more respect could be shown to people who are just trying to get the best outcomes.

John
+1
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Old 7th December 2019, 12:56 AM   #135
Terry Demol is offline Terry Demol  Australia
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Quote:
Originally Posted by chris719 View Post
Do you have any info on AK4137's DPLL bandwidth or behavior, or filter responses?
Chris, I contacted AKM about this ages ago and the support engineer was not
able to come up with any info.

Same with ComTrue ASRC (forget the part no).

T
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Old 11th December 2019, 11:18 PM   #136
adam1016 is offline adam1016  United States
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Made some changes to the I/V stages so that they hopefully more resemble the schematic, however I find the schematic provided in the evaluation manual essentially unusable. It's been a lot of effort to get it into something more readable from the mess of wires they give you. The old link should still be good, here it is again:
AK_DAC.pdf - Google Drive
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Old 11th December 2019, 11:42 PM   #137
Markw4 is offline Markw4  United States
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Adam,
Probably no need for 4-wire control. Basically, its a version of SCI bus.
I2C bus should be fine for everything, IMHO.

Differences basically are that SCI can run much faster, but it has a Select line for each device on the bus which can add up to a lot of select lines.

I2C is slower (although fast enough for us) and is device addressable so that only two wires and ground can be shared by several devices.
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Old 11th December 2019, 11:45 PM   #138
adam1016 is offline adam1016  United States
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Markw4 - As soon as I have my copy of the schematic matching the Úval board, the 4 wire bus is going to be one of the first things to go. Just want to get to a “known state” where my schematic is identical to the eval board.
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Old 12th December 2019, 12:16 AM   #139
Markw4 is offline Markw4  United States
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Okay, understood

Also, a typo correction: I should have typed SPI bus (not SCI).
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