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Making an I2S R2R DAC with a FPGA
Making an I2S R2R DAC with a FPGA
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Old 18th November 2019, 12:55 PM   #21
edbarx is offline edbarx  Malta
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Join Date: May 2018
If the glitch is at the end of digital to analogue conversions, a clock pulse at twice the sampling frequency can be used to sample the output from the resistance ladder in the middle of every sample. This avoids the glitch altogether. For this, a sample and hold circuit could be used.

This is something, I never tried, but it is logical.
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