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Grossly parallel multibit DAC adventures
Grossly parallel multibit DAC adventures
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Old 12th October 2019, 06:14 AM   #1
abraxalito is offline abraxalito  United Kingdom
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Default Grossly parallel multibit DAC adventures

During my development of TDA1387-based DACs I came to the tentative conclusion that fewer chips was generally better in SQ terms. That was based on experience that strongly hinted that the power supply was the limiting factor and that more chips meant heavier demands on the supply. I also found that more output current made an I/V stage (other than a purely passive one) harder to get sounding good.

The power supply sensitivity turned out to be in large degree dependent on the variation in output voltage at the DAC's current outputs - purely passive I/V usually has the largest output voltage variation, consequently the highest sensitivity to power supply rail noise. By 'noise' here I don't just mean random noise, normally load-induced (i.e. signal correlated) noise is a bigger influencer of SQ.

A 'lightbulb' moment came when I considered that a step-up transformer could be used to ensure a very low voltage variation at the DAC's output whilst still allowing a high enough I/V resistor to be used so as not to need a voltage gain stage to create a 2VRMS output signal. Use of a step-up transformer isn't new, Audio Note had a patent on it (now expired). What is new is using a high ratio step-up transformer in conjunction with a very large number of paralleled DAC chips - the parallel array allows an even smaller variation of DAC output voltage and hence lower power supply sensitivity.

I've attached an outline sketch of the arrangement. A large number of paralleled DACs generates a peak current in the region of a few tens of mA. The DAC arrays are arranged to generate that current in 'push-pull' mode (aka 'balanced') so that there isn't any need to block the DC through the trafo - the DC currents are applied out of phase and hence cancel within the core of the trafo. The secondary of the trafo has typically 100X the turns of the primary meaning the standard 2VRMS is generated directly from 20mV at the DAC and only needs filtering (to attenuate images) and buffering to create a low output impedance for driving cables and a power- or pre- amp.

From my earliest experiments with a step-up transformer, I found that the primary inductance is what creates the LF roll-off and that the usual core material I use (PC40) doesn't give enough inductance (or have high enough mu in other words) to give an optimized design. So I have moved over to using 10K material which has about 4X higher mu but a lower peak flux capability. There aren't too many forms of core that this 10K material turns up in (at least in off-the-shelf quantities) on Taobao, I have for my earliest public design settled on using EP17. The wish to create a fully balanced design means using two EP17s per channel, for a total of 4. Fortunately they're cheap to buy on Taobao, the main cost is going to be in the labour to wind them.

Gerbers are attached for a 36 DAC board - four of these are needed to feed into the 4 EP17 transformers so that the output created is 2VRMS across the I/V resistors. In the sketch the output filter's shown single-ended but for the first design I'm going balanced, necessitating doubling up on filter and buffers, leading to a transformer between the two phases for creating a single-ended output.
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File Type: jpg 446236268.jpg (117.3 KB, 920 views)
Attached Files
File Type: zip Gerber_PCB DenaDAC.zip (154.4 KB, 22 views)
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Last edited by abraxalito; 12th October 2019 at 06:29 AM.
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Old 15th October 2019, 07:18 AM   #2
abraxalito is offline abraxalito  United Kingdom
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Default Lower complexity design - Q-gross DAC

Since soldering up four DAC boards and interconnecting them is really only for the true hair-shirt brigade of multibit die-hards (myself very definitely included) I was wondering if it would be possible to design a 'gateway DAC' based on this model but which called for far fewer DAC chips. Turns out, it is and I have the first prototype playing into my ears as I type. This will eventually allow a DAC to be built using just two PCBs - as soon as the PCB layout for the analog board gets done, anyway

The lower number of DAC chips comes at a price as there are no free lunches and its paid in terms of the output compliance voltage at the DAC chips. The trafo of the Q-gross (quarter-gross) DAC has only a 1:25 step up ratio so ~40mVRMS exists at those pins, whereas on the 4 PCB design, that's down to ~10mVRMS as the transformer gives 100X voltage gain. The analog PCB is agnostic towards the number of DAC chips used, the difference will just be in the winding details of the EP17 trafos used. In theory its possible to accommodate even more than 144 TDA1387s although I've yet to figure out a way of fitting the thicker wire on the transformer's bobbin. There has to be some way though.....

In the photo, the analog board containing CLC filters, trafos and buffers is at the rear - it feeds into RM10 cores (rear right) wound as output bal-SE trafos. The DACs themselves are fed from a TL431 shunt at 4V and the whole is powered from a single 6V rail.
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Old 15th October 2019, 07:35 AM   #3
nautibuoy is offline nautibuoy  United Kingdom
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Quote:
Originally Posted by abraxalito View Post
Since soldering up four DAC boards and interconnecting them is really only for the true hair-shirt brigade of multibit die-hards (myself very definitely included)...
I admire your tenacity but doesn't there come a point where the sensible thing would be to make the investment in a reflow oven based soldering regime?

Where are you getting all the TDA chips?
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Old 15th October 2019, 07:56 AM   #4
abraxalito is offline abraxalito  United Kingdom
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As I set out on the lingDAC thread, I'm not sure that a reflow approach would in fact be more efficient in time. Partly because I prefer to test the DACs first, with only power applied and partly because these chips are already desoldered and they're not mechanically consistent from part to part as fresh parts off the reel would be. They have excess solder on many pins and on the sides of the package which sometimes leads to shorts between pins. The pins are also bent out of shape in many cases so they're not all in contact with the PCB which makes me wonder if they'll be amenable to reflow.

The chips are from Taobao.
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Old 15th October 2019, 08:11 AM   #5
analog_sa is online now analog_sa  Europe
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Grossly parallel multibit DAC adventures
Quote:
Originally Posted by abraxalito View Post
From my earliest experiments with a step-up transformer, I found that the primary inductance is what creates the LF roll-off
This would be resolved if the i/v resistor is on the primary side of the transformer and loads the dacs outputs directly, right?
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Old 15th October 2019, 08:19 AM   #6
abraxalito is offline abraxalito  United Kingdom
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No, not according to my simulations in LTSpice - the LF roll-off was the same. But the LF gain gets reduced by the ratio between the I/V resistor's value and the DCR of the primary which was something of a surprise, given I'm still a greenhand in working with trafos. Meaning a primary with significantly lower R than the I/V resistor is needed to transmit all the output current of the DACs to the secondary.
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Old 15th October 2019, 11:11 AM   #7
canvas is offline canvas  Taiwan
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Hi Richard,

Have you tried transformer I/V after the current mirror? I'm currently applying a 10k:10k transformer after OPA861. It has DCR around 2k, so I don't need the I/V resistor. Due to the limited swing voltage of OPA861, I have to trim the output voltage by paralleling a resistor on the primary side. The trafo also takes care of the LPF, so minimum parts are used here.

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Old 15th October 2019, 12:21 PM   #8
abraxalito is offline abraxalito  United Kingdom
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Poting - no, I'm not using any kind of active circuitry in current mode. Simply a buffer (an EF biassed by a CCS) fed from the I/V resistor. Entirely passive prior to the I/V. In my experience a trafo as LPF is a bit hit-and-miss in that the leakage inductance (which provides the series element of an LC filter) is difficult to predict and has rather large variation.
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Old 15th October 2019, 02:05 PM   #9
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Grossly parallel multibit DAC adventures
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Originally Posted by abraxalito View Post
No, not according to my simulations in LTSpice - the LF roll-off was the same.
How do you represent the DAC output? A voltage source in series with a resistor? How big a resistor?
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Old 15th October 2019, 02:24 PM   #10
abraxalito is offline abraxalito  United Kingdom
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The DAC output is a current source, so I use an LTSpice current source. The output impedance of the DAC I've tried to measure but it turned out to be too high to get a precise measurement (>1Mohm) so I've not used a resistor in parallel with the CS.
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