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Grossly parallel multibit DAC adventures
Grossly parallel multibit DAC adventures
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Old Yesterday, 10:18 AM   #121
sajunky is offline sajunky  South Africa
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Location: Johannesburg
Quote:
Originally Posted by abraxalito View Post
Yeah, give 'em a go. You'll need at least 36 to build the Q-grossDAC.

The variations of labelling I've seen are these 4.
Highly suspicious. From your pic the second from left looks fake as well.
Logo is subject to the copyright laws. There are two ways to avoid litigations. Make a logo to look inrecognizable or remove logo completely.

EDIT: Font is different. Font design is also subject to copyright laws.

Last edited by sajunky; Yesterday at 10:23 AM.
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Old Yesterday, 11:15 AM   #122
sajunky is offline sajunky  South Africa
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Quote:
Originally Posted by abraxalito View Post
I've pondered this idea @sajunky and I can't think of any advantage of spreading out the 36 DAC chips over two boards rather than one. Perhaps if they were running above 5V and getting warm this would allow them to run cooler by spacing them apart. Or perhaps if you wanted to get the maximum sample rate out of them you could do this as the HC86 which drives them doesn't have very high drive ability when running at 2.5V as in this design. But a better solution might be to raise its supply voltage (change the LED which is a shunt reg to a higher voltage one) so as to improve its drive ability. Going much above 3.3V (not sure which LED would give this mind, perhaps remove the shunt LED and run direct from the DAC supply) you'd want to swap HC86 for HCT86 to preserve logic level compatibility on the I2S inputs.

You're right, the extra cost of two PCBs is going to be relatively small, given how cheap PCBs are these days.
You look from a designer point of view. Yes, it can be better. Always we can make it better... However I don't want to distract you from releasing a final project, I want my kit shipped now , now , now and what I do propose doesn't change a design.

Yes, you seem have overlooked the fact that there is lot of 192kHz source for download. Also the optimal conversion rate from SADC (DSD64) and DSD128 source is 176.4kHz. TDA 1387 chip can handle much more. We discussed it already and I was satisfied from your report that with the current filter setting sample rate 88.4kHz brings minimal deviation to the frequency plot, the same probably with 96kHz. If someone wants to go 176.4/196kHz, (I want to try), then spreading out 36 DAC chips over two boards would help clocking these chips properly with reduced jitter. Some others would like to use bypasing film capacitors, there is more space to do so.

It was a discussion running already. This time I wanted to show that spreading out chips has practical advantage. It is easier to find a fault. Owners of H-DAC version would perhaps want to keep a fifth board as a spare. Replacing a faulty board is quicker than finding a fault on the board.
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Old Yesterday, 11:40 AM   #123
abraxalito is offline abraxalito  United Kingdom
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Location: Hangzhou - Marco Polo's 'most beautiful city'. 700yrs is a long time though...
Quote:
Originally Posted by sajunky View Post
You look from a designer point of view.
Well yeah, duh

Quote:
Yes, it can be better. Always we can make it better... However I don't want to distract you from releasing a final project, I want my kit shipped now , now , now and what I do propose doesn't change a design.
So long as your kit is the most basic level one (nothing pre-assembled at all) then yeah, this doesn't change the design.

Quote:
Yes, you seem have overlooked the fact that there is lot of 192kHz source for download.
Wouldn't that all be 192k/24 rather than 192k/16 though?

Quote:
Also the optimal conversion rate from SADC (DSD64) and DSD128 source is 176.4kHz.
First I've heard of that - got any links I can follow to learn up on why this would be so?

Quote:
TDA 1387 chip can handle much more. We discussed it already and I was satisfied from your report that with the current filter setting sample rate 88.4kHz brings minimal deviation to the frequency plot, the same probably with 96kHz.
Maybe a boost in the FR of 1 to 2dB at the top end.

Quote:
If someone wants to go 176.4/196kHz, (I want to try), then spreading out 36 DAC chips over two boards would help clocking these chips properly with reduced jitter.
Yep, but then why stop at removing half the chips? Taking 75% of them off will reduce jitter even more (only half serious).

Quote:
It was a discussion running already. This time I wanted to show that spreading out chips has practical advantage. It is easier to find a fault. Owners of H-DAC version would perhaps want to keep a fifth board as a spare. Replacing a faulty board is quicker than finding a fault on the board.
I'm not sure I follow that its easier to find a fault. But maybe it is as even with 36 chips you can start by isolating which board - which is the first stage of a binary search. But then you're down to individual chips.

Btw - if you really really don't want to distract me, keep what you actually plan to do off the thread, at least until kits are available

Oh and regarding fake chips, there are 5 different variants of the one you reckon is a fake on my desktop. That's not proof of course but renders it less likely its a faked one.
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Last edited by abraxalito; Yesterday at 11:44 AM.
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Old Yesterday, 05:04 PM   #124
sajunky is offline sajunky  South Africa
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Quote:
Originally Posted by abraxalito View Post
So long as your kit is the most basic level one (nothing pre-assembled at all) then yeah, this doesn't change the design.
That is a main point, just a BOM for an extra PCB.

Quote:
Originally Posted by abraxalito View Post
Wouldn't that all be 192k/24 rather than 192k/16 though?
It depends on the NV data content of USB bridge. Device driver will expose device capabilities to the user. The best if it matches capabilities of our DAC chip. Generic USB bridges will expose maximum capabilities of the USB chip instead, but we can select sample rate and bit depth either on the DS control panel or in the app when working in WASAPI exclusive mode. Everything above 16-bit is accepted as 16-bit (ignoring number of LSB's), but a clock rate is increasing wasting bandwith.

Quote:
Originally Posted by abraxalito View Post
First I've heard of that - got any links I can follow to learn up on why this would be so?
I can find links saying that DSD quality is comparable with 24/88.2kHz PCM, some say it is higher, but nobody wants convert DSD content to 44.1kHz with a lot of ultrasonic content, it is for sure. For the purpose of this thread I will end on this assessment.

Quote:
Originally Posted by abraxalito View Post
Maybe a boost in the FR of 1 to 2dB at the top end.
It was noted already and fully accepted.

Quote:
Originally Posted by abraxalito View Post
Yep, but then why stop at removing half the chips? Taking 75% of them off will reduce jitter even more (only half serious).
Simple calculation for a clock load. If a given clock works fine with 36 chips @96kHz, then reducing load capacitance in half is expected to work @ a double rate. It is not enough, as higher sampling rate requires a lower jitter. I could further demand for 1/4 (9 chips), but I want to try 18 chips first.

Quote:
Originally Posted by abraxalito View Post
I'm not sure I follow that its easier to find a fault. But maybe it is as even with 36 chips you can start by isolating which board - which is the first stage of a binary search. But then you're down to individual chips.

Btw - if you really really don't want to distract me, keep what you actually plan to do off the thread, at least until kits are available
.LOL. Of course I will bring sensitive matters in private and I promise, it will never come out.
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