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My no DAC project. FPGA and transistors.
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Old 11th August 2019, 10:06 PM   #11
MarcelvdG is offline MarcelvdG  Netherlands
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OK, so you did clip off amplitude noise. I'm surprised that your active probe works poorly at close carrier offsets, as I would expect an active probe to produce additive noise. Apparently it is nonlinear enough to have some mixing effect going on between its low-frequency noise and the carrier.
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Old 11th August 2019, 10:44 PM   #12
JohnW is online now JohnW  Hong Kong
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Active probes are designed for greatest B/W, so feature the smallest possible geometry devices on the input stage (Lowest IP capacitance = Highest B/W).

The Close-in noise of active probes when used in there linear range is purely thermal/ shot noise, nothing to do with "mixing effects"... just as with any Diff stage when operated in its linear range...

Active probes also have Highish value series resistors internally to help limit the current into the protection circuits during over-voltage events - these series resistors also add noise...

As would be expected we find slower active probes have better close in noise performance - we put this down to maybe larger input devices...

As I mentioned, where Phase Noise is really critical then we use passive Diff probes if circuit loading conditions allow... On some designs we have a pair of SMB positions on clock line on the PCB to facilitate PN measurements - thus avoiding noise issues with Diff probes.

We have a selection of Active High speed diff probes from Agilent / Tek from 1GHz to 12GHz and non standout as better or worst then others, but the general rule is lower B/W, better close in PN...
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Old 11th August 2019, 11:04 PM   #13
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by JohnW View Post
The Close-in noise of active probes when used in there linear range is purely thermal/ shot noise, nothing to do with "mixing effects"... just as with any Diff stage when operated in its linear range...
Then why isn't it additive?
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Old 12th August 2019, 04:10 AM   #14
xx3stksm is offline xx3stksm  Japan
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My no DAC project. FPGA and transistors.
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Originally Posted by mterbekke View Post
Nice work indeed!

Maybe the oscillation problems are due to having to build the cml output yourself. OnSemi has a cml building block that might solve this:
I guess the oscillation is due to many differential amplifiers(24taps). It becomes unstable when the DSM signal changes its state(H to L or L to H), where both transistors are simultaneously active. It automatically stops the oscillation when both are not in an active state.I haven't yet found an effective way to stop the oscillation.
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Old 12th August 2019, 04:17 AM   #15
xx3stksm is offline xx3stksm  Japan
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Originally Posted by mterbekke View Post
Would you mind sharing the resistor values for R1 to R4?
No problem. R4=15,c39=5p,R1=15,C38=0,R2=R6=150,R3=R5=680//4700p.But they are subject to change since the circuit is under developping. OPA1612 is more prefferable than ADA4004 or ADA4998.
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Old 12th August 2019, 04:58 AM   #16
xx3stksm is offline xx3stksm  Japan
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Originally Posted by JohnW View Post

Your confusing Skew with Phase noise - they are not related. You can have a bunch of outputs all perfectly matched edges - but this says NOTHING about there phase noise.
Yes, I agree with you that both are a different matter. I'm not pessimistic about FPGA jitter because my measurement is relatively positive, though my measurement environment isn't ideal. The 1st pic is the famous jittery clock, IIS of Rpi(MDO3102 and TAP1500). I can't believe it can be a DAC clock. But as long as your DAC is multibit, this doesn't have fatal degradation. If your DAC is DSM, your noise floor could be around 16bit resolution. The 2nd is SPDIF recovered clock by CS8416. Harmonics of 48kHz is due to 48kHz sampling. This is also not excellent.

The 3rd pic is the clock of my 1bitDSM board. This is after two I/Os because the clock passes through another FPGA before it arrives the 2nd FPGA which has DSM process and transistor drivers. It's not perfect but far more better than the 1st pic and the 2nd. I'm on the application side, not on the manufacturer side. What I can say is how much jitter is acceptable in a particular application. FPGA jitter in not ideal condition doesn't have fatal degradation on DSM at least up to x128OSR as long as I have experienced.

Another example for FPGA jitter is DDR3 application. This is a guideline for DDR3, where you need excellent jitter performance since it has 800MHz clock at max.
https://china.xilinx.com/support/doc...dr3-si-pcb.pdf
It shows some eye pattern with jitter. When your DDR3 application has a successful result, FPFA I/O must satisfy the requirement of DDR3. Spartan6 can handle DDR3 interface, though you need careful consideration to implement it into FPGA, including PCB layout. Tha's why I'm sure jitter of spartan6 is acceptable in DDR3. So is in x128OSR DSM
Attached Images
File Type: jpg Rpi.jpg (233.0 KB, 383 views)
File Type: jpg CS8416.jpg (223.3 KB, 376 views)
File Type: jpg ck_FPGA.jpg (213.5 KB, 371 views)
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Old 12th August 2019, 08:37 AM   #17
mterbekke is offline mterbekke  Netherlands
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Quote:
Originally Posted by xx3stksm View Post
I guess the oscillation is due to many differential amplifiers(24taps). It becomes unstable when the DSM signal changes its state(H to L or L to H), where both transistors are simultaneously active. It automatically stops the oscillation when both are not in an active state.I haven't yet found an effective way to stop the oscillation.
Thanks! That clarifies a lot. The onsemi building block (do check it if you haven't yet pls), is basically what you built but monolithic: so you don't have to fiddle with current sources, and you keep control over r1 etc, because it has an open drain/collector output.
This might very well solve the oscillation problems, while you don't lose functionality and have better matching etc.
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Old 12th August 2019, 08:47 AM   #18
mterbekke is offline mterbekke  Netherlands
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To xx3stksm & MarcelvdG:

I'm thinking that all JohnW is trying to say is that if the reclocking after the fpga's are left out, all someone else needs to do is copy xx3stksm's basics, add some flip flop's, claim better performance and all your time and effort has been for someone else's fame and fortune. That's low hanging fruit there that needn't nor shouldn't be there, except for blind faith in fpga building blocks.
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Old 12th August 2019, 12:32 PM   #19
JohnW is online now JohnW  Hong Kong
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Quote:
Originally Posted by xx3stksm View Post
That's why I'm sure jitter of spartan6 is acceptable in DDR3. So is in x128OSR DSM
An easy assumption to make, but what is important is the frequency content (Spectrum) of the PN.

Communications / Data systems set there PN measurement corner frequency too high for audio applications - typically 12KHz or higher, making there Jitter specs. useless for audio applications - most systems have VERY poor close in phase noise due to high PLL BW, poor oscillator Q, noisy low power logic design, etc.

If you look at the PN performance of Logic family's I attached ealier you can see that ECL has worst Close-in Phase noise compared to most CMOS family's, bench testing shows LVDS is even worst.

To get a better understanding of the "ball park" Jitter performance we require with Simple Maths (There are many factors that determine the absolute jitter requirement, but such basic math gets us more or less in the correct "Decade"):-

1 bit SDM at x128 FS= 5.6448MHz = 177nS

Lets set a target of 120dB Dynamic range (1 millionth), so we need to be able to reproduce our pulse stream with a short term timing accuracy of 177nS / 1,000,000 = 177fS

177fs assumes 100% modulation, at max we have say 50%, so:-

177fS/2 = 88fS

88fS is a crude "Off the cuff" calculation and does NOT take into account many details, but its a good starting point to appreciate the Jitter requirements to achieve 120dB DR with a pure 1bit system at 128FS...

Moving average DAC array arrangements / higher SDM bits ease these PN requirements, but thats getting into the finer details...

The point is you need to forget shooting for pS short-term jitter performance, but you need to be in the low fS range...

"Short-term" means over say 5 - 10 seconds to bring the Close-in noise slope (area) down to a decent level...

What I'm trying to impress upon you is that the typical Jitter performance corner frequency spec'ed from 12KHz is useless for our discrete Audio DAC array applications - you need to be thinking about timing accuracy in a different realm to normal industry standards (In B/W and level).

Measuring Close in Phase noise with the required Dynamic range is extremely difficult and expense - when higher performance measurements are required, we have a whole RACK of computer controlled equipment to performance the task, but the system still sets the industry standard for close in Phase noise measurements (the system has been upgraded since the picture was taken):-

Dropbox - Phase nosie measurement system.jpg

Heres the systems confidence test (basically the systems Noise floor):-

Dropbox - Agilent E5500 System Confidence Test.jpg

(Again the Mains related spuire is due to magnetic coupling of background fields into the system).

I said once before here on this forum that working with Discrete SDM DAC design is frustration but also the most educational experience a "Digital" audio designer can undertake I designed my first commercial discrete SDM DAC back in 1990/1991 (Pink Triangle Dacapo) and still to this day rely on the design fundamentals I learnt back then. I can honestly say that as a Digital audio designer, its was the most concise learning period of my whole career
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Last edited by JohnW; 12th August 2019 at 12:50 PM.
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Old 12th August 2019, 02:04 PM   #20
xx3stksm is offline xx3stksm  Japan
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Quote:
Originally Posted by mterbekke View Post
Thanks! That clarifies a lot. The onsemi building block (do check it if you haven't yet pls), is basically what you built but monolithic: so you don't have to fiddle with current sources, and you keep control over r1 etc, because it has an open drain/collector output.
This might very well solve the oscillation problems, while you don't lose functionality and have better matching etc.
Thank you for the feedback. I also googled several monolithic modules to eliminate the complexity of discrete components. What I did consider was the noise power of the current source. NB4N11M has 16mA one(fig.18). The current has no PSRR like power rail of Signalyst topology. You usually can't predict how much noise power it has. The only way to control the noise power is a simple current source by a transistor as I posted before. Base voltage(BIAS_N) driven by LT3042 is the major factor to determine the noise power. If you fail to select a clean current source, your prototype PCB becomes a mess. Discrete components are inconvenient but have flexibility. That's the very reason why I chose discrete transistors in my first try. After two months of struggle, I can say now it's not a bad selection. It has very low noise power because of LT3042 and easy to change the current(from 3mA to 5mA is optimum). I would say the oscillation is a trade-off for low noise power.
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