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My no DAC project. FPGA and transistors.
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Old 20th November 2019, 10:50 PM   #161
mterbekke is offline mterbekke  Netherlands
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Originally Posted by JohnW View Post
You introduce more conversion (linearity) error without RTZ on a pulse by pulse basis then you do by the extra edge transitions (as there should be) with correct RTZ conversion.
Thnx! In general I look at this error as data correlated noise (and distortion), enhancing the edge speed (20 pS) and not having such big voltage swings also helps the time edges need, hence the sonic non-rtz winner here.

I'm building a 4-Flip Flop dac, which can be made to work as an stereo interleaved dac element, a 4 channel dac or a stereo dual fir. Front end is not ready yet to accomodate all of this, but at least this part is ready to go to the pcb manufacturer soon and there'll be room to experiment to check all this.

Your last picture shows 4 volt bulk caps, any particular reason to go for a 3v3 supply when you can go for 5 or even 6 volts?

Soldering techniques looking aok to me, great work and excellent measurement results indeed, very nice to see this!
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Old 20th November 2019, 11:03 PM   #162
JohnW is offline JohnW  Hong Kong
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Originally Posted by mterbekke View Post
Your last picture shows 4 volt bulk caps, any particular reason to go for a 3v3 supply when you can go for 5 or even 6 volts?
Caps where only mounted for photo , the array on this design operates at 4.5V as the design is USB powered and we struggle with the 500mA USB current limit, although we will still be a little over......

The larger Array design operates at upto 6V1...

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Originally Posted by mterbekke View Post
Soldering techniques looking aok to me, great work and excellent measurement results indeed, very nice to see this!
Thank you, however:-

If you look closely you can see damage to the solder resist + uneven size of solder on each pad, but the results of the "Quick" test was that I can work with such small packages... Although I do worry about the larger array as its not easy to QC each solder joint (as they are under the package) and the larger array has many more packages... We have an PCB XRay machine in the lab, but its not something you want to use for each PCB - the array covers a large and its not easy to QC each individual PCB joint...

I'm just programming the P&P machine so I hope better results from machine built boards.... I REALLY hope...!

Measurement where from a larger array design (8 element), the simple two element array design PCB I'm currently building will have lower performance - I expect a DNR of somewhere between 118dB to 124dB and a FS THD of say 110dB...

A 124dB dynamic range would be great as it would match the results of our designs using ES9038Q in Dual diff (limited by the noise of the analogue output stage used on our budget designs).

Keen for the results ASAP
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Last edited by JohnW; 20th November 2019 at 11:10 PM.
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Old 21st November 2019, 05:23 AM   #163
xx3stksm is offline xx3stksm  Japan
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Originally Posted by JohnW View Post

Any DAC array design will become more sensitive to Master Clock Phase noise with more edge transitions (increased clock rate) by 20LogN with N being the clock rate increase, ie 6dB more sensitive to MCLK Phase noise with a doubling of clock frequency.

We use FIR analogue filtering on the DAC array WITH RTZ encoding (well atleast on the larger array designs) - with ANY pulse DAC design if you dont normalises the energy contribution of each "pulse" you will incur THD+N, its unavoidable due to the error of finite edge times - the ONLY method I'm aware to remove the error introduced by real world applications is to implement RTZ.
Thank you very much for your detailed information. Are A7AJ and N9AB a high-speed logic gate with galvanic isolation? Then high OSR(512 or 1024) DSM pulse train with FIR analog filtering is fed to the analog stage. What I still can't understand is coexistence with FIR analog filter, which is probably the same meaning as analog FIR that I use for my no DAC.

Analog FIR in my project means the sum of 1bitDSM pulse train with one clock delay. The attached pic is 42taps analog FIR in 4th order DSM(128OSR). It has vertical 28 resolutions; amplitude usage is 28/42=67%. High order(8th) is usually around 50%. The more, the better if you want excellent SNR. 4th order is theoretically superior to 8th as long as out of band noise is ignored.

I have tried several times to use RTZ encoding but failed to have good results. High OSR and the digital process of RTZ aren't difficult, where much advantage exists because they are in the digital domain. As long as I know, RTZ goes back to zero before the next pulse to ensure the same pulse energy. The very problem is all tap becomes zero before the next pulse. The center position of the attached pic is 21 if the coding is NRZ; the sum of 21 ones and 21zeros results in 21. If you use RTZ in 3 to 1(3/4 is one, 1/4 is zero), 3/4 period is 21; it's the same as NRZ. But 1/4 period is 0 because all tap is zero. The lowest position of the pic is 7(21-14=7). 0 means you can't have an analog-like sine wave like the pic, which means distortion. That's why I can't employ RTZ. I guess I have a fatal misunderstanding. But I couldn't find the answer yet why RTZ can coexist with analog FIR. Please correct me if I'm wrong.
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Old 21st November 2019, 05:33 AM   #164
MarcelvdG is offline MarcelvdG  Netherlands
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You can get rid of the gaps when you make the pulses 0 for half the clock period, apply half-cycle delays between taps (for example by alternating rising and falling edge clocking) and make sure that there are always two taps with the same weight.
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Old 21st November 2019, 06:10 AM   #165
xx3stksm is offline xx3stksm  Japan
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Thank you for your feedback. I have understood RTZ in 1 to 1(1/2 is one, 1/2 is zero) with half-cycle delay can get rid of the gap. But I guess RTZ in 1 to 1 has less amplitude usability, which means less SNR. I don't know RTZ can outperform NRZ in numbers. Anyway, I need to learn more about RTZ. Thanks.
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Old 22nd November 2019, 09:43 PM   #166
mterbekke is offline mterbekke  Netherlands
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Originally Posted by MarcelvdG View Post
You can get rid of the gaps when you make the pulses 0 for half the clock period, apply half-cycle delays between taps (for example by alternating rising and falling edge clocking) and make sure that there are always two taps with the same weight.
Wouldn't that be totally depending on the duty cycle, inverting clock = inverting the duty cycle = changing the timing of the addition of the alternating energy packets?
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Old 22nd November 2019, 10:51 PM   #167
MarcelvdG is offline MarcelvdG  Netherlands
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Indeed, but in the most usual implementations the widths of the pulses depend in the same way on the duty cycle as the delays. In fact this is why you need pairs of taps with (nominally) equal weights, so that random variations of the duty cycle will not (or hardly) affect the sum.

For example, with eight taps:
clock high: output signal = weighted sum of taps 1, 3, 5 and 7, the rest is made zero
clock low: output signal = weighted sum of taps 2, 4, 6 and 8, the rest is made zero

When taps 1 and 2 have equal weights and the same holds for 3 and 4, for 5 and 6, for 7 and 8, and the shifting arrangements are made properly, the exact position of the falling edge within each clock cycle ideally doesn't affect the output signal.

(In practice random duty cycle variations will still modulate the position of the switching spike between the odd and the even taps, but that has much less impact than random duty cycle variations have in a single RTZ DAC.)
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Old 22nd November 2019, 10:52 PM   #168
mterbekke is offline mterbekke  Netherlands
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Originally Posted by xx3stksm View Post
Thank you very much for your detailed information. Are A7AJ and N9AB a high-speed logic gate with galvanic isolation? Then high OSR(512 or 1024) DSM pulse train with FIR analog filtering is fed to the analog stage. What I still can't understand is coexistence with FIR analog filter, which is probably the same meaning as analog FIR that I use for my no DAC.

Analog FIR in my project means the sum of 1bitDSM pulse train with one clock delay. The attached pic is 42taps analog FIR in 4th order DSM(128OSR). It has vertical 28 resolutions; amplitude usage is 28/42=67%. High order(8th) is usually around 50%. The more, the better if you want excellent SNR. 4th order is theoretically superior to 8th as long as out of band noise is ignored.

I have tried several times to use RTZ encoding but failed to have good results. High OSR and the digital process of RTZ aren't difficult, where much advantage exists because they are in the digital domain. As long as I know, RTZ goes back to zero before the next pulse to ensure the same pulse energy. The very problem is all tap becomes zero before the next pulse. The center position of the attached pic is 21 if the coding is NRZ; the sum of 21 ones and 21zeros results in 21. If you use RTZ in 3 to 1(3/4 is one, 1/4 is zero), 3/4 period is 21; it's the same as NRZ. But 1/4 period is 0 because all tap is zero. The lowest position of the pic is 7(21-14=7). 0 means you can't have an analog-like sine wave like the pic, which means distortion. That's why I can't employ RTZ. I guess I have a fatal misunderstanding. But I couldn't find the answer yet why RTZ can coexist with analog FIR. Please correct me if I'm wrong.
I look at RTZ as a amplitude shift. There's just less amplitude (and less low frequency modulation).

So you're saying that because with RTZ there's many times that the FIR runs empty (all zero's)?

But per same time (integrated) it's the same time duration of zero's, right?

Also, at first glance you'd expect RTZ to be able to go to higher modulation depth than, let's say 67% (less lower frequency modulations because of the alternating 1's at low rates, less ISI), but as you said: the zero's are constantly full on.

I'm guessing that this is one of the reasons why John advocates for differential signals, I'd like to know if there needs to be carefull matching of these differential signals (or if distortion levels at high modulation depth go down when matched better).

The main drawback of RTZ is the need for a higher bitclock. For jitter this seems to be great because of the faster edges of the XO, for low phase noise not so.
Would like to know how all of you correlate/solve those higher phase noise clocks vs jitter?
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Old 22nd November 2019, 11:45 PM   #169
mterbekke is offline mterbekke  Netherlands
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Quote:
Originally Posted by MarcelvdG View Post
Indeed, but in the most usual implementations the widths of the pulses depend in the same way on the duty cycle as the delays. In fact this is why you need pairs of taps with (nominally) equal weights, so that random variations of the duty cycle will not (or hardly) affect the sum.

For example, with eight taps:
clock high: output signal = weighted sum of taps 1, 3, 5 and 7, the rest is made zero
clock low: output signal = weighted sum of taps 2, 4, 6 and 8, the rest is made zero

When taps 1 and 2 have equal weights and the same holds for 3 and 4, for 5 and 6, for 7 and 8, and the shifting arrangements are made properly, the exact position of the falling edge within each clock cycle ideally doesn't affect the output signal.

(In practice random duty cycle variations will still modulate the position of the switching spike between the odd and the even taps, but that has much less impact than random duty cycle variations have in a single RTZ DAC.)
I wholeheartedly agree, but now it's getting almost philosophical: the idea once was to let go of having to match power supply levels, resistors, temperatures etc and let every piece of silicon add to the signal. DSD does just that. Once you divide it into sectors (odd and even) and have to weigh those later you're almost back to square one.

Of course, it's not as bad as a good ol' thermometer DAC, and this is a good solution to the problem, but I also see it as a step back.

Choices choices. So many of them, right?!

Has anybody ever tried to use a clock signal and pass it to the output when data signal = 1 and otherwise not? It would just mean to have a good switch, or a logic AND. There'll always be a 0 after it etc.

Btw aren't you describing the interleaved dac? I read it has much less hf noise, but don't know why.

Have a good weekend you all!
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Old 23rd November 2019, 07:05 AM   #170
xx3stksm is offline xx3stksm  Japan
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Quote:
Originally Posted by mterbekke View Post
I look at RTZ as a amplitude shift. There's just less amplitude (and less low frequency modulation).

So you're saying that because with RTZ there's many times that the FIR runs empty (all zero's)?

But per same time (integrated) it's the same time duration of zero's, right?

Also, at first glance you'd expect RTZ to be able to go to higher modulation depth than, let's say 67% (less lower frequency modulations because of the alternating 1's at low rates, less ISI), but as you said: the zero's are constantly full on.
The modulation depth of DSM depends on the order. The best is the 1st or 2nd order DSM, which can have almost 100%. As long as I have experienced, 3rd is 75%, 4th is 65%, 5th is 55%, and more than 6th is 50%. Less modulation depth means less SNR because the signal can't be large while noise is the same level. The maximum amplitude of DSM is usually smaller than PCM by 6dB(50%) because of high order DSM(more than 6th). RTZ has another burden because of the inherent zero. If RTZ is 1 to 1(50% duty cycle), a half is always zero, which results in another 6dB loss; total signal loss is 12dB(if more than 6th order). So, I want to use at least RTZ with3 to 1(2.5dB loss instead of 6dB), but the gap caused by inherent zero isn't avoidable unless you use RTZ with 1 to 1(6dB loss).

I don't know if RTZ can outperform NRZ or not. I have been an NRZ person in my DSM career. That's why I will play with NRZ for the time being. I'm sure the correct IO pad assignment of FPGA is promising. If I could find a way that has additional improvement on SNR by 1dB, my goal(120dB SNR) is truly achievable with NRZ.
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