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My no DAC project. FPGA and transistors.
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Old 19th November 2019, 06:29 AM   #151
xx3stksm is offline xx3stksm  Japan
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My no DAC project. FPGA and transistors.
Quote:
Originally Posted by mterbekke View Post
Not sure about what can be achieved on the real pcb regarding signal quality. 30 pS is a low figure with fpga, but you'd have to be really precise about impedance controll and trace length to stay in that region on pcb level. It's a great feature that with fpga you can controll timings this precise, it gives room to adjust which gives it an edge over just hoping pcb traces will work out. What steps/resolution can the fpga provide?
The reason I dived into 1bitDSM is high potentiality even if it is implemented in discrete components. 1bit DSM itself doesn't have good numbers like my previous post; ordinary THD+N and large out of band quantization noise. I employed CML to convert digital pulse to the analog signal. The very meaning isn't a small switching voltage but moderate PSRR. Signalyst topology is usually 0dB PSRR, where a very clean power rail is mandatory, and probably large voltage is superior to a small one. CML is the current switch directly driven by a digital stream of 1bit DSM. But analog signal across collector has some isolation from the dirty digital stream of 1birDSM. In other words, you have some PSRR because of the constant current character of a transistor, which means at least 30dB. I need to emphasize this is a significant advantage of CML, though fewer implementation exists in no DAC project, AFAIK. I guess your high estimation of CML comes from some PSRR, which ensures high SNR.

The disadvantage of CML is instable(easy to oscillate) and difficult to maintain phase alignment between taps. I have now managed to control the oscillation problem, though it depends on the real PCB; another PCB must have another solution. Phase alignment also has been resolved by "FPGA hacking." I can control the relative propagation delay between taps(skew), the attached pic. Two nets are beyond 0.6ns. But careful IO physical assignment can fix the problem, though my current PCB has the wrong IO assignment. I'm sure the final PCB with the correct assignment has successful phase accuracy, even in 48taps.

My current PCB has 36taps with correct phase relation(36taps out of 48 taps). 36taps is a little bit short of arriving at 120dB SNR, almost 118dB. Clock jitter is also a dominating factor in obtaining high SNR. PLL inside FPGA has phase adjustment ability and excellent stability because of high internal frequency(1GHz). As far as I have experienced, IO buffer jitter is 30ps, clock jitter is 50ps, and phase alignment between taps(skew) is 100ps. That's why I always emphasize the phase alignment. The former two are device oriented; you can't change physical restriction. The phase alignment is up to you. The best value is probably 50ps.
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Old 19th November 2019, 06:44 AM   #152
xx3stksm is offline xx3stksm  Japan
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We use CMOS UHS to speeds of DSD 4096.. (200MHz).... Although be prepared for very high power dissipation at these clock speeds... Above 200MHz we use PECL...
Hi, JohnW. This is an interesting thread opened recently, though I guess you already know it.
STAR Pure DSD DAC-Signalyst New

The numbers(94dB THD and 94dB SNR) are almost the same as I have experienced before in Signalyst topology. I'm sure the point is 0dB PSRR. I highly appreciate it if you share the measurement result on your no DAC. It's very surprising and exciting for me if Signalyst topology(0dB PSRR) has more than 100dB SNR.
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Old 19th November 2019, 09:31 PM   #153
JohnW is online now JohnW  Hong Kong
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The "Signalyst topology" can never achieve high technical performance for many reasons, but the first is the lack or RTZ encoding, there will always be a systematic linearity error - just as any DAC array that does not insure each pulse's "energy" contribution is discrete and independent from the proceeding and next pulse.

PSRR is not an issue, just careful PSU design (and balanced operation) is required, you are after all simply integrating the PSU rail directly (with all its Noise etc).

Not a criticism of the "Signalyst topology" its simple, its crude on many levels, but has the potential of sounding VERY good... depending on modulator far better then any commercial DAC from ESS etc..

I've got our latest 2 element DAC PCB in the SMT P&P machine - I expect results by the weekend (once I complete the PCB build and Software) - I'll post the here (As only two Array elements performance will be less then a larger array design, but we still expect DNR about 118dB, and THD better then 110dB).

Results of a larger 8 element array at -20dB, Ref 4VRms (Balanced) 256fs 1bit modulator:-

Dropbox - Discrete SDM Array -20dB Zoom FFT.jpg - Simplify your life

Analogue stage above is "standard" Opamp (not transformer based) hence lower THD, although at these levels (-20dB) transformers can be very linear...

I'll post pictures and results of the latest PCB at the weekend if all goes well.
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Old 20th November 2019, 05:05 AM   #154
xx3stksm is offline xx3stksm  Japan
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Thank you for your reply. I was under the impression that you use a kind of Signalyst topology. I couldn't imagine the way to improve performance in this case. I have understood your topology is an entirely different one, though I have no idea about your architecture. What I can guess is the similarity to Chord's performance. They use pulse array technology, which I don't know in detail. As long as I know, a large array is better than a small one. You also say 8 elements array is better than 2 elements, though I can't understand what element means.

I guess your topology prefers high OSR and RTZ encoding. High OSR is very sensitive to clock jitter, while low OSR(x64) isn't so. That's why you emphasize low phase noise to ensure extreme low jitter. I know different topology has its pros and cons. I usually use low OSR(x64 or x128) and NRZ because analog FIR dislikes a large number of pulse toggles and can't coexist with RTZ. I'm sure our destination is the same, but the route to the goal is different. It's inspiring that there are many routes to the summit. I'm looking forward to seeing your result.

P.S. How many FFT sizes you use in the attached pic? I guess 512k or 1024k.
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Old 20th November 2019, 08:12 AM   #155
mterbekke is online now mterbekke  Netherlands
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Quote:
Originally Posted by JohnW View Post
I'm afraid that the subject RTZ is very miss-understood here on the forum, with a whole load of rubbish spouted I cannot it even get my head around to understand.

RTZ function is to insure that the energy contribution of each pulse is independent on the previous or next pulse... The pulse is returned to zero before the next pulse cycle.

Without RTZ you will have increased THD + Noise as there is an inherent system non linearity - which unless you have infinitely fast pulse edges cannot be resolved...

The ONLY requirement is that each individual pulse - think packet of energy (Positive or Negative) has EXACTLY the same energy contribution over time.

The important point to note is that the shape of the pulse is not important - just that the energy contribution of each pulse remains identical - you could have one pulse triangle shaped, the next pulse rectangle - just as long as their energy density (pulse area) is the same and they have no effect on the previous or next pulse your system will be linear.
I think the misunderstanding ranges from sloppy writing to total misunderstanding of the subject.
If only we could tag the information in these threads we'd have a excellent databank..

What are your thoughts on the jitter sensitivity regarding rtz, or do you look at it as being solved (largely/completely) by using many taps/an interleaved structure etc?
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Old 20th November 2019, 08:13 AM   #156
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Quote:
Originally Posted by JohnW View Post
Results of a larger 8 element array at -20dB, Ref 4VRms (Balanced) 256fs 1bit modulator:-
congrats!
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Old 20th November 2019, 08:22 AM   #157
mterbekke is online now mterbekke  Netherlands
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Quote:
Originally Posted by xx3stksm View Post
The reason I dived into 1bitDSM is high potentiality even if it is implemented in discrete components. 1bit DSM itself doesn't have good numbers like my previous post; ordinary THD+N and large out of band quantization noise. I employed CML to convert digital pulse to the analog signal. The very meaning isn't a small switching voltage but moderate PSRR. Signalyst topology is usually 0dB PSRR, where a very clean power rail is mandatory, and probably large voltage is superior to a small one. CML is the current switch directly driven by a digital stream of 1bit DSM. But analog signal across collector has some isolation from the dirty digital stream of 1birDSM. In other words, you have some PSRR because of the constant current character of a transistor, which means at least 30dB. I need to emphasize this is a significant advantage of CML, though fewer implementation exists in no DAC project, AFAIK. I guess your high estimation of CML comes from some PSRR, which ensures high SNR.

The disadvantage of CML is instable(easy to oscillate) and difficult to maintain phase alignment between taps. I have now managed to control the oscillation problem, though it depends on the real PCB; another PCB must have another solution. Phase alignment also has been resolved by "FPGA hacking." I can control the relative propagation delay between taps(skew), the attached pic. Two nets are beyond 0.6ns. But careful IO physical assignment can fix the problem, though my current PCB has the wrong IO assignment. I'm sure the final PCB with the correct assignment has successful phase accuracy, even in 48taps.

My current PCB has 36taps with correct phase relation(36taps out of 48 taps). 36taps is a little bit short of arriving at 120dB SNR, almost 118dB. Clock jitter is also a dominating factor in obtaining high SNR. PLL inside FPGA has phase adjustment ability and excellent stability because of high internal frequency(1GHz). As far as I have experienced, IO buffer jitter is 30ps, clock jitter is 50ps, and phase alignment between taps(skew) is 100ps. That's why I always emphasize the phase alignment. The former two are device oriented; you can't change physical restriction. The phase alignment is up to you. The best value is probably 50ps.
How do you get to these timings, do you measure these with a scope, do you calculate it from trace length and do the rest by thd+n measurements?

Seems like a pretty hard puzzle.

Great thing is that once you figure out the pcb the rest can be optimized from the desktop
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Old 20th November 2019, 12:33 PM   #158
xx3stksm is offline xx3stksm  Japan
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Default old technology

There is specification about clock jitter of internal PLL on the datasheet, and you can directly measure the jitter with a scope or FFT analyzer. It's probably 50ps. You can't find the specification about the uncertainty of the IO buffer. The available one is the propagation delay. 30ps is my rough estimation, which means less than clock jitter. Skew between taps is also measurable with a scope. Another way to estimate is simulation data: my previous post. They are the perfect ones.

The autorouter, which is a default setting in large scale FPGA, isn't suitable to have accurate phase relation because they are not optimized for such purpose. You need to do manual routing for better matching, which is out of date technology in 21 century. I used to do manual routing in the early '90s when I began to design a digital circuit with FPGA. Nobody uses manual routing these days, including me. But old forgotten technology is necessary to adjust phase relation between taps. The attached pic is the FPGA editor to do manual routing and LUT assignment. I have understood the principle why some IO pad can have less than 0.5ns delay, while some can't. Unfortunately, my IO pad assignment was incorrect. I can fix the problem when I design the next PCB because the FPGA editor guides me to have the correct IO pad assignment for 48 taps. Ancient tech is sometimes useful.
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Old 20th November 2019, 10:08 PM   #159
JohnW is online now JohnW  Hong Kong
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Quote:
Originally Posted by xx3stksm View Post
Thank you for your reply. I was under the impression that you use a kind of Signalyst topology. I couldn't imagine the way to improve performance in this case. I have understood your topology is an entirely different one, though I have no idea about your architecture. What I can guess is the similarity to Chord's performance. They use pulse array technology, which I don't know in detail. As long as I know, a large array is better than a small one. You also say 8 elements array is better than 2 elements, though I can't understand what element means.
Each DAC "element" requires a pair of datalines from the FPGA Modulator and as they are galvanically isolated on our designs, the array size has a big impact on the designs complexity and cost!

For the latest array design we have used leadless packages to reduce the arrays physical size, in fact each "element" has a low impedance decoupling capacitor mounted ABOVE the packages in a 3D style build...

Picture of one "Element" - I hand mounted the packages to gain some experience of manual reworking these tiny leadless packages, so soldering is not great...

Dropbox - DAC Array Element.png - Simplify your life

With the Bulk low impedance Capacitors mounted above "Dac" Element:-

Dropbox - DAC Array Element with Cap.png - Simplify your life

Quote:
Originally Posted by xx3stksm View Post
I guess your topology prefers high OSR and RTZ encoding. High OSR is very sensitive to clock jitter, while low OSR(x64) isn't so. That's why you emphasize low phase noise to ensure extreme low jitter. I know different topology has its pros and cons. I usually use low OSR(x64 or x128) and NRZ because analog FIR dislikes a large number of pulse toggles and can't coexist with RTZ.
Any DAC array design will become more sensitive to Master Clock Phase noise with more edge transitions (increased clock rate) by 20LogN with N being the clock rate increase, ie 6dB more sensitive to MCLK Phase noise with a doubling of clock frequency.

We use FIR analogue filtering on the DAC array WITH RTZ encoding (well atleast on the larger array designs) - with ANY pulse DAC design if you dont normalises the energy contribution of each "pulse" you will incur THD+N, its unavoidable due to the error of finite edge times - the ONLY method I'm aware to remove the error introduced by real world applications is to implement RTZ.

Quote:
Originally Posted by xx3stksm View Post
P.S. How many FFT sizes you use in the attached pic? I guess 512k or 1024k.
8192 points over the 5K span... the Max FFT size the older Rohde & Schwarz UPD can do is 16K points over 20KHz so I tend to use Zoom FFT to look closer at the area of interest as there is nothing of interest to see above the 5KHz span to 20KHz so I might was well increase the measurement resolution where "something" is going on...

We have later UPV's in the lab and they can perform 1 Million point FFT's but I much prefer the older UPD "UI" and the UPD has lower noise floor (at the same number of FFT points) with its ADC notch filter enabled.
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Last edited by JohnW; 20th November 2019 at 10:33 PM.
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Old 20th November 2019, 10:14 PM   #160
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Quote:
Originally Posted by mterbekke View Post
What are your thoughts on the jitter sensitivity regarding rtz, or do you look at it as being solved (largely/completely) by using many taps/an interleaved structure etc?
You introduce more conversion (linearity) error without RTZ on a pulse by pulse basis then you do by the extra edge transitions (as there should be) with correct RTZ conversion.
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