I interested your DAC side. Are you ready to share the schematic and code for FPGA for testing and evaluation !?Your attached pic is probably R2R(PCM) ladder DAC architecture. It's possible to drive R2R both with a discrete logic(HC590) and with a differential amplifier(your pic). But 1bitDSM with a differential amplifier is a bit different from the R2R ladder. One tap of 1bitDSM is independent of others: one is already complete DAC. Paralleling taps means averaging to achieve better performance. A discrete device(HC590) is also configured as 1bitDSM. All the more reason to avoid a discrete one for me is noise performance. You can't get rid of noise from the power rail because no PSRR exists as long as you use discrete logic. If you use a differential amplifier instead of discrete logic, you have some PSRR because it acts as a current switch. I don't know why some 1bitDSM can have excellent SNR despite discrete logic. I guess it's their secret.
As to the sound quality, I haven't finished soldering eight DACs which is necessary for my system. What I can say is if you are a classical music listener, poor SNR is fatal. That's the reason why I design 1bitDSM with a differential amp. I have some experience with poor SNR 1bitDSM. It's terribly bad for music with pianissimo.
The Digital section(oversampling and two 5th order DSMs) is here.
Simple DSD modulator for dsc2
Source code isn't open because the object file is enough for a DIYer. The analog section is still under construction. I'm considering if PWM like mola mola is possible. There is a chance to be open when I finish fixing the design. NRZ architecture works fine but a little bit difficult to implement unless you design it yourself.
URL is here.
Simple DSD modulator for dsc2
Simple DSD modulator for dsc2
Source code isn't open because the object file is enough for a DIYer. The analog section is still under construction. I'm considering if PWM like mola mola is possible. There is a chance to be open when I finish fixing the design. NRZ architecture works fine but a little bit difficult to implement unless you design it yourself.
URL is here.
Simple DSD modulator for dsc2
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Yes, everyone has their opinion. I don't ask someone to give me an answer. What I want is the principle. How to design hardware logic to be compatible with the principle is my curiosity. So, I can't understand why they need source code(an answer). What you need is the principle or block diagram if you are a DIYer. That's the reason my code isn't to be open.
I don't ask someone to give me an answer. What I want is the principle. How to design hardware logic to be compatible with the principle is my curiosity. So, I can't understand why they need source code(an answer). What you need is the principle or block diagram if you are a DIYer. That's the reason my code isn't to be open.
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I have not figured out what is the best architecture in the analog domain yet. I'm still at the experimental level. It's impossible to share because there is no fixed schematic. But the digital domain is a bit different. The project by olo111 inspired me that the digital domain could be one function itself as PCM2DSM converter. I'm now redesigning my ADC with the AD7768 and xc6slx9. It's going to have HDMI-IIS I/O because recent DACs have HDMI-IIS input for PCM and DSD. It would be helpful if ADC has HDMI-IIS to do synchronous sampling. As long as I have experienced it, HDMI-IIS input is the best solution for such DACs. USB isn't the best scenario due to the wrong clock recovery(D90).
If so, it's easy to utilize my ADC as a PCM2DSM converter with HDMI-IIS. You can use it as PCM to DSM bridge for D90 or other DACs with HDMI-IIS. This includes the digital domain only. I can share my DSM for such a purpose.
If so, it's easy to utilize my ADC as a PCM2DSM converter with HDMI-IIS. You can use it as PCM to DSM bridge for D90 or other DACs with HDMI-IIS. This includes the digital domain only. I can share my DSM for such a purpose.
I see what you're saying, but there are tons of HDL guides and courses on the internet. Most would be better suited to learning than just looking at the VHDL or Verilog for this project. Plus this project is using Spartan 6 which requires ISE, and if you are new to Xilinx you probably don't want to waste your time learning things you'll have to unlearn because ISE is dead.
I suspect if he posted the source this would end up in someone else's product. Whether he cares or not is another matter.
Regarding HDMI dac interfacing, there is a very interesting resource at:
i2s - Google Drive ...Tabs at the top of the page select the connector type of interest.
i2s - Google Drive ...Tabs at the top of the page select the connector type of interest.
Yes, everyone has their opinion.
many folks gots inspiration by the work of others... I have discovered many aspect of some matter that was of my interest by taking a peek of what approach someone has taken, and what was not choosen.
So, to from my pov, an open approach for a comunity that is based around the share of knowledge is always beneficial.
If your only interested is the answer, then you have alredy had one... if that is your only concern, then why not sharing ?
but you are in full right of doing what you want
I agree with xx3stksm.
It is not "creative" food making DIY.
.
It is hard theese days to determine what is diy in fact?
Because of many different area is involved.
Especially with sogtware-hardware combinations.
.
From technological point of wiew this is not a DIY specimen.
- PCB is complicated many hard to solder parts for 95% or more DIYers.
- special soldering tools, skils and experience needed.
- hard to apply code. Probably need a special additional hardware interface to bridge the computer and PCB?
- dedicated software for "burning" the code. Probably original and payed...
- because of good chrs, testing of "finished" module deserves expencive soundcard interface?
- there will be many "how to questions" for xx3. Sometnihng is not working. Morte time than bulding the code...
- there are a great chances that code will be "used" (stolen). And many working hours will be gone...
...
It is not "creative" food making DIY.
.
It is hard theese days to determine what is diy in fact?
Because of many different area is involved.
Especially with sogtware-hardware combinations.
.
From technological point of wiew this is not a DIY specimen.
- PCB is complicated many hard to solder parts for 95% or more DIYers.
- special soldering tools, skils and experience needed.
- hard to apply code. Probably need a special additional hardware interface to bridge the computer and PCB?
- dedicated software for "burning" the code. Probably original and payed...
- because of good chrs, testing of "finished" module deserves expencive soundcard interface?
- there will be many "how to questions" for xx3. Sometnihng is not working. Morte time than bulding the code...
- there are a great chances that code will be "used" (stolen). And many working hours will be gone...
...
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I had a chance to ask an excellent programmer a question about why hardware code isn't so open compared with software. He said, "hardware doesn't make sense without material things, which means some cost(someone's profit) even if code is free. Software isn't. If the software is open, it's already done. No cost means no someone's profit." It's true.
it's irrelevant, no matter how much you spend on the hardware, it is completely independent from what people who wrote code?
this is current steering model?if you use current steering in discrete device dac ,the Beta of transistors is diffrent between transistors,so the current is diffrent between tapsThe latest analog section(pic.1 and pic.2) is slightly different from post #1. No specific bias is required because FPGA I/O swings from zero to 1.3V. I have measured several hundred transistors' Vbe and found no significant difference; no need to select. Beta is ignorable if Vbe is the same in a differential stage by a transistor.
The converted signal across R78 and R22 has only a simple op-amp buffer; no op-amp differential stage now. If you use a discrete device(HC590) instead of transistors, it's very tricky to have excellent SNR. I tried it several times but failed and gave up such architecture. Replacing HC590 with transistors also failed. Many trials and errors couldn't bring me a successful result: the zero PSRR trap.
P_42 and N_42 are differential pairs driven by FPGA I/O. Three transistors differential amp is non-saturation switching architecture, where no current fluctuation exists except transition time: the shorter transition, the better. FPGA I/O has many options, slew rate, drive power, and swing voltage. Pic.3 is probably the best scenario. Less than one nano sec transition time with slight ringing is very challenging. I'm sure only FPGA I/O can complete the job because it has enough VCC and GND pads to output a stable pulse.
Furthermore, an internal PLL can adjust the skew between positive and negative output by 0.1 nano sec. Such preciseness implies better jitter performance; probably 30 pico at max. The skew is entirely a critical factor to have perfect conversion. Fast and ringing less switching with fine adjustment is the point to have excellent performance.
Yes, while the emitter current remains the same, the collector current can deviate slightly due to variations in β. In practical terms, with β around 100 or so, the deviation is around 3%, roughly equivalent to 0.03%. 2sc5662 has very uniform β and Vbe values, making even unsorted components yield such figures. There aren't many components that offer this level of consistency. In a discrete setup, with resistor precision at around 0.1%, considering this as equal doesn't make an issue.
When individually measuring each tap, THD varies between 90dB and 110dB. SNR remains mostly consistent. In a monolithic design, individual variations would likely be even smaller. Some taps may not reach 90dB, and in those cases, a slight adjustment of the base resistor can lead to improvement. Replacing transistors might not yield favorable outcomes, likely due to significant influences from the driving side, such as differences in rise and fall time.
When individually measuring each tap, THD varies between 90dB and 110dB. SNR remains mostly consistent. In a monolithic design, individual variations would likely be even smaller. Some taps may not reach 90dB, and in those cases, a slight adjustment of the base resistor can lead to improvement. Replacing transistors might not yield favorable outcomes, likely due to significant influences from the driving side, such as differences in rise and fall time.
Have you thought about using a darlington and possibly a dissimilar darlington. By this I mean that one BJT (a) is chosen for high beta or current (will have higher Cob) and the second (b) is chosen for ultra low Cob and high speed.
The two work in a way that can leverage the better properties of each. The higher beta BJT (usually higher Cob) is the 'slave' the fast, low Cob BJT is the 'master'. Together the beta will be very high, the Cob losses very low but still have VG linearity.
TCD
The two work in a way that can leverage the better properties of each. The higher beta BJT (usually higher Cob) is the 'slave' the fast, low Cob BJT is the 'master'. Together the beta will be very high, the Cob losses very low but still have VG linearity.
TCD