I have seen people worrying that I2S source can contain glitches in the timing ruining the signal. I wonder how much it would help if there is a retiming chip in the signal path?
Said retiming chip can be implemented using a CPLD like EPM240T100C5N. The CPLD implements a FIFO-based asynchronous bridge, capable of holding a few samples in its internal buffer, and have two clocks from each side. This would break the clock domains, allowing the DAC/ADC to run on its own low jitter clock while the rest of the digital processing can run on its own PLL clock. As long as the clocks on each side matches close enough, it would not suffer from overflows.
Said retiming chip can be implemented using a CPLD like EPM240T100C5N. The CPLD implements a FIFO-based asynchronous bridge, capable of holding a few samples in its internal buffer, and have two clocks from each side. This would break the clock domains, allowing the DAC/ADC to run on its own low jitter clock while the rest of the digital processing can run on its own PLL clock. As long as the clocks on each side matches close enough, it would not suffer from overflows.
How much of a buffer? What is clock frequency delta?
200ppm difference leads to 9 samples/s drift ar 44.1k Fs, if my math is correct.
So, in underflow case, you'll get 9Hz glitches. In overflow, with 3sample buffer, 3Hz.
You need real memory and lil bit of signal analysis to make it work. The tightest one would be around 10-20 kbyte for 44kHz 24bit data. Anything less will have glitches.
200ppm difference leads to 9 samples/s drift ar 44.1k Fs, if my math is correct.
So, in underflow case, you'll get 9Hz glitches. In overflow, with 3sample buffer, 3Hz.
You need real memory and lil bit of signal analysis to make it work. The tightest one would be around 10-20 kbyte for 44kHz 24bit data. Anything less will have glitches.
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Now make it $5
I don't think I can make it within the $5 budget, but $15 may work if I skim on some support components.
This shouldn't be an issue as an I2S bus has a single clock source, the I2S master. Issues arise when connecting two different pieces of equipment each with an I2S bus perhaps? That requires clock synchronization or a large-enough FIFO to solve - either completely coupling or completely decoupling the clocking domains. And strictly speaking that scenario is not related to I2S at all.
Now make it $5
$5 not, but $10 is possible, if we are talking just about BOM cost of I2s->I2S module in 10-100pcs quantity: STM32F4xx or similar starts from $6 and required just few R and C. Plus PCB and assembly, of course.
This is getting really silly. In order to improve most i2s sources a set of good clocks are needed together with a really low noise PS. $70 seems to be the absolute minimum in parts this far. And obviously the reclocking should be done outside the FPGA.
The FPGA and micro are just not cost considerations for such a project.
The FPGA and micro are just not cost considerations for such a project.
Like this one?
STM32F030F4P6 CORTEX-M0 ARM 32 Bit 48MHz Core Mini USB Board Development Sy N0Z3 664984655306 | eBay
As for the oscillators, you could still slap TL431 and *U04 together. (not all of 431s are equal)
The oscillators and reclocking should be on DAC's board anyway, so it's not a concern of I2SI2S module.
The only use of these I2SI2S modules is to clean-up PLL/synth based clock sources (vintage USB, SPDIF, codecs, media players and, huh, DSP boards).
They are bad, much worse than a can of oscillator in crude-soldered nest of wires
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