8 × AK5578EN + 8 × AK4499EQ ADC/DAC Boards

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Here you go, another block diagram (Figure 1) that represents how AK4499 and similar parts operate. Note the DAC (and everything after the SAI) is clocked by MCLK.

https://statics.cirrus.com/pubs/appNote/AN306REV1.pdf

This is also your answer to the ESS question, because in a way, the ESS approach with ASRC is very similar to Figure 2 and how the cheap Cirrus and TI DACs that have integrated PLLs to recover the MCLK operate.
 
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Updated USB and DAC Boards

Here are some updated USB and DAC boards for which the seven regulators (5 NJM78M05 and 2 SMD versions of the BA033CC0T) are mounted directly on the PCB. This will ensure that we do not deviate from the original design of the evaluation board, while reducing the height of the DAC assembly. It will also reduce the BoM of a single DAC board by a cool $90...

The DAC board is certainly a tight fit, and many resistors and capacitors will have to be mounted on the underside. We might also go from 70mm × 35mm to 72mm × 36mm in order to get a tiny bit of extra breathing room. That being said, I really like the layout as it stands.

The isolated part of the USB board has now been broken down into three sections:

1. Oscillators (bottom right with picture in portrait orientation)
2. Outputs (right)
3. Inputs (top)

As a result, the pins located on the top side and used for isolated inputs will not be used by the DAC board, but they could be used by some other boards. This will ensure that we can reuse the USB board across different bricks.

The four balanced outputs on the DAC board are now provided through four separate sets of three pins, which is probably better than two sets of six pins. That being said, their actual positions might evolve a little bit as we finalize the overall component placement.

On the DAC board, we now have 16 pins for the audio inputs and 16 pins for the controls, which will allow us to provide separate ground references for everything we need, but we lost the two extra GPIOs that we had included in an earlier iteration.

Now that we have a high-level validation of the overall design, we will review every single component of the AK4499EQ evaluation board in order to come up with a full BoM. And when that part is done, we will do the same for the USB board.
 

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DAC Board BoM

We have listed all the components for the DAC board on its BoM sheet. This leaves us with a few questions:

- What is the maximum voltage for the 180pF C8, C9, C19, C20, C56, C57, C58, and C59 capacitors?
- What is the maximum voltage for the 0.1μF C39, C40, C41, C42, C47, C48, C68, C69, C70, C75, C80, and C81 capacitors?
- Is R1 a 5.1Ω resistor or a 5.1kΩ resistor?
- What is R7?
 
The LT3045 data sheet shows the recommended board layout in the applications section. You should read the entire applications section carefully to make sure you understand the issues.

Mark,

I just finished reading the manual for the DC2491A demo board of the LT3045. The Kelvin connection method using the split capacitor technique is awesome! And the input trace directly above the return path to cancel EMFs is beautiful. I really wish that all components were so precisely documented and supported by such clean reference implementations... It makes me want to use this component just for the sheer beauty of the circuitry involved.

Thanks a lot for the nudge!
 
I really wish that all components were so precisely documented and supported by such clean reference implementations... It makes me want to use this component just for the sheer beauty of the circuitry involved.

It is not done for beauty's sake of course. Its just that high performance circuits require careful design in order to minimize errors. If a very high level of performance is of no particular benefit, then no need to waste time and money. Find where the problems are and focus on improving those those things.
 
It is not done for beauty's sake of course. Its just that high performance circuits require careful design in order to minimize errors. If a very high level of performance is of no particular benefit, then no need to waste time and money. Find where the problems are and focus on improving those those things.

For an engineer, these are words of wisdom. But the artist wants to see beyond...
 
I posted a block diagram of a relatively modern delta sigma DAC which shows the switched capacitor DAC clocked directly from MCLK. If anyone's repeating the same thing over and over, it would be you :). This isn't a matter of my opinion, the DAC is just clocked by MCLK.

Yes you did. The diagram shows the rates that the various parts of the DAC run at and shows the required clock signals for the final parts of the conversion process. It does not however show explicitly that the MCLK is what dictates the start of the conversion process.

The reference to start the conversion is MCLK. The actual DAC operates at the oversampled rate that is the output rate of the DSM. I am waiting for your explanation as to how the actual converter can be clocked at Fs or 64*Fs (word and max bit clock rates) when the DAC rate is 128 or 256*Fs.

I've never said that the converter is clocked at fs or whatever. Where you've come up with this idea I do not know as it shows a breakdown in communication. Either you've not understood what I've said or you've not read what I've written.

What I've said is that the high speed operation of the DS DAC requires the MCLK to work but that the LR clock is used as the timing reference that tells the DAC when to convert data.

I am not sure why you can't see that the clock for the converter can be phase independent of the clocks used to clock the data into the digital filters. There are these structures called registers / buffers, you know. This is all still in the digital domain.

I've said before that I am aware of buffers/input registers, did you choose to ignore this?

You are right that the MCLK absolute phase isn't important, but it still must be frequency locked. You are reading into that statement and coming up with an incorrect conclusion.

The reason why I can't see the separation of the two is because the exact timing of when each subsequent word should be processed is contained within the rising edges of the LR clock. As there is no phase relationship between the rising edges of the LR clock and the MCLK this exact moment is lost if you were to use the MCLK for timing alone.

Because ESS uses an ASRC... so there is not an input MCLK accompanying the input stream.

That wasn't the point I was trying to make. The point was that the exact timing of when to process the data is highly important and that without a phase relationship between the LR clock and MCLK you can't simply rely on the MCLK to define this moment.

The ESS paper itself compares the effect of jitter present on the data lines with a standard DS DAC to the effect on the ESS DAC. Obviously the ESS DAC separates the incoming data from the incoming data clock and resamples, so any jitter present on the data lines is irrelevant. But the paper clearly shows that this has a negative effect on a normal DS DAC.


Like I said, if this simple yes/no test doesn't do it for you, please start with explaining how the internal DAC can be clocked at a rate higher than the bit clock or word clock if it is clocked by bit clock or word clock as you maintain. If there were an internal PLL or FLL to multiply those clocks, then why would there even need to be an MCLK input?

I am not saying that the internal DAC is clocked by the data clocks.

What I am saying is that the MCLK runs the high speed sections of a DS DAC. But that the LR clock is used as the timing reference for when to start processing the data bytes within the DAC itself. Obviously the conversion isn't instant with a group delay involved from the input to output.

I will read those links later.
 
I am not saying that the internal DAC is clocked by the data clocks.

What I am saying is that the MCLK runs the high speed sections of a DS DAC. But that the LR clock is used as the timing reference for when to start processing the data bytes within the DAC itself. Obviously the conversion isn't instant with a group delay involved from the input to output.

I will read those links later.

What you are saying makes no sense. I think you have a fundamental misunderstanding and I can't even tell exactly where/what it is. I am done here, but know that you are 100% wrong. I don't have more time to waste on this, you can lead a horse to water... :)

MCLK or a directly divided version of MCLK drives the conversion process directly. You still can't answer my simple questions, instead you jump to the incorrect conclusion that the DAC's analog output changes with edges of LRCK (which it does not).

Edited to elaborate further:

So, we've gotten past bit clock and data jitter being important it seems (you implicitly agree with this if you agree that another clock drives the converter).

You seem to be hung up on this:

"the exact timing of when to process the data is highly important and that without a phase relationship between the LR clock and MCLK"

This is not important. The data is deserialized with it, but after that, it's no longer important. Everything afterward is clocked from MCLK or a divided version of MCLK. Only the frequency relationship is important for most of these parts. The datasheets say this.

Just answer this question - how can the DAC elements be 5-bit, 6-bit, whatever the multi-bit final converters are, and be clocked at LRCK rate? Where do you think this faster clock comes from?

Nothing matters except the clock that drives the actual conversion. Nothing.
 
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Chris,
I think maybe some of the problem above has to do with how the clocking hand off from LRCK in the case of PCM, or BCLK in the case of DSD, gets passed over to MCLK. In other works if MCLK is at arbitrary phase with whatever input clock is used, how is it guaranteed there isn't false triggering at the hand off due to simultaneous clock edges.

My guess would be there is a probably short FIFO somewhere with asynchronous inputs and outputs. So, maybe LRCK for PCM, or BLCK for DSD, clocks the FIFO input and MCLK clocks the output. If you think it would help, you could describe what you think it is in more detail.
 
Chris,
I think maybe some of the problem above has to do with how the clocking hand off from LRCK in the case of PCM, or BCLK in the case of DSD, gets passed over to MCLK. In other works if MCLK is at arbitrary phase with whatever input clock is used, how is it guaranteed there isn't false triggering at the hand off due to simultaneous clock edges.

My guess would be there is a probably short FIFO somewhere with asynchronous inputs and outputs. So, maybe LRCK for PCM, or BLCK for DSD, clocks the FIFO input and MCLK clocks the output. If you think it would help, you could describe what you think it is in more detail.

Yep, you are probably right. There is almost certainly a small buffer/FIFO, which is how you are allowed to have MCLK phase independence. The frequency relationship is required otherwise you would be risking underrun / overrun.

We can also look to how the old PCM1702/PCM1704 functioned. PCM1702 performs an update of the analog output on the 4th rising edge of BCK after a falling edge of LE (mono word clock). That makes BCK the important clock for this chip. Not that I think the modern converters do this exactly, but it shows how you can move data through the DAC without the word clock being the "critical" clock.

Further empirical evidence is that you can effectively clean jitter with an ASRC chip. If modern delta-sigma converters were affected by jitter on LRCK and BCK, then this would not have as much of an impact. The ASRC outputs a new LRCK and BCK, but it's still the output of a (relatively) noisy, active digital IC - you probably aren't getting state of the art phase noise out of the pins of an AD1896/SRC4192, even if it's just dividing the clock you fed in. Yet somehow, the J-Test signal results of DACs using them are basically pristine despite their LR and Bit clocks going through at least one complicated logic IC. In many others, those same clocks go through an FPGA too.

For DSD, the BCK is an important clock for converters that do direct conversion.
 
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Regulator Board

I know that I should not obsess over the regulators for the VDD supplies, but I simply cannot help it. Somehow, I find this LT3045 linear regulator strangely attractive. Furthermore, the DAC board needs to be redesigned, because it is too densely packed. Together, the NJM78M05 and the 470μF capacitor take about 100mm² of surface area, and we need 5 sets, which means 500mm². On a 70mm × 35mm board (2,450mm²), that's over 20% of the board's surface!

Therefore, the idea of mounting regulators on discrete boards is quite attractive: doing so, each board only takes 4 headers (about 25mm² for each board), and heat can be dissipated more effectively. Not only does this approach reduces the footprint of the regulators on the board by 80%, but it breaks down this footprint into pairs of pairs of headers, making it much easier to optimize the placement of components on the board.

Over the past few days, I have spent a lot of time studying the datasheet and demo manual for the LT3045, as well as the modules sold by LDOVR, and I have come to the conclusion that we should design our own. There are several reasons for it:

- We need a layout like this one instead of that one
- We should be able to make the board much smaller (30mm × 15mm)
- We need a 470μF CIN capacitor instead of 47μF
- We could add a WE-SHC shielding cabinet
- We could optimize our heat dissipation design
- We could use this board for many different bricks
- We would learn a lot doing this small and relatively simple project

Here is the BoM for this REG board (less than $10 per board). The board will be designed so that its components face the DAC's components. As a result, the underside of the board will face the underside of the brick's cover. This arrangement will allow the regulator boards to be screwed to the brick's aluminum cover, thereby providing a great source of heat dissipation.

Finally, we will take advantage of this project to learn more about thermal vias.

These boards will be used for the 4 VDD supplies as well as the AVDD and TVDD supplies, thereby replacing the BA033CC0T voltage regulator. Also, we might design a larger board that would include both an LT3045 and an LT1963 in order to provide the +3.3V TVDD and the +1.8V DVDD supplies that we need. The LT1963 is used by the AK4499EQ evaluation board and by the OSVA AAPSU01, therefore we will need to study it in details anyway. This would give us the following incremental roadmap:

1. LT3045 regulator board
2. LT3045 + LT1963 regulator board
3. LT8609A + LT3471 + LT1965 + TPS7A47/TPS7A33 PSU board
 
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I know that I should not obsess over the regulators for the VDD supplies, but I simply cannot help it. Somehow, I find this LT3045 linear regulator strangely attractive. Furthermore, the DAC board needs to be redesigned, because it is too densely packed. Together, the NJM78M05 and the 470μF capacitor take about 100mm² of surface area, and we need 5 sets, which means 500mm². On a 70mm × 35mm board (2,450mm²), that's over 20% of the board's surface!

Therefore, the idea of mounting regulators on discrete boards is quite attractive: doing so, each board only takes 4 headers (about 25mm² for each board), and heat can be dissipated more effectively. Not only does this approach reduces the footprint of the regulators on the board by 80%, but it breaks down this footprint into pairs of pairs of headers, making it much easier to optimize the placement of components on the board.

Over the past few days, I have spent a lot of time studying the datasheet and demo manual for the LT3045, as well as the modules sold by LDOVR, and I have come to the conclusion that we should design our own. There are several reasons for it:

- We need a layout like this one instead of that one
- We should be able to make the board much smaller (30mm × 15mm)
- We need a 470μF CIN capacitor instead of 47μF
- We could add a shielding cabinet
- We could optimize our heat dissipation design
- We could use this board for many different bricks
- We would learn a lot doing this small and relatively simple project

Here is the BoM for this REG board (less than $10 per board). The board will be designed so that its components face the DAC's components. As a result, the underside of the board will face the underside of the brick's cover. This arrangement will allow the regulator boards to be screwed to the brick's aluminum cover, thereby providing a great source of heat dissipation.

Finally, we will take advantage of this project to learn more about thermal vias.

These boards will be used for the 4 VDD supplies as well as the AVDD and TVDD supplies, thereby replacing the BA033CC0T voltage regulator.

You might be overthinking the parts of it that don't need overthinking :).

I'll give you another option to consider. This is a very new part that I only stumbled on because I've been looking for LDOs that come in packages that are 1 square mm or less:

https://www.onsemi.com/pub/Collateral/NCP161-D.PDF

It also comes in SOT-23 if you need something you can hand solder without reflow.

I *highly* doubt you need a 470uF electrolytic as an input cap for each 7805 for a DAC digital supply. The AKM apps guys might be crazy for all we know, or it covered up some other deficiency. I always look closely at eval boards and schematics and try to gauge the quality to know how closely I should follow it. This one has some weird stuff...
 
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You might be overthinking the parts of it that don't need overthinking :).

I'll give you another option to consider. This is a very new part that I only stumbled on because I've been looking for LDOs that come in packages that are 1 square mm or less:

https://www.onsemi.com/pub/Collateral/NCP161-D.PDF

It also comes in SOT-23 if you need something you can hand solder without reflow.

I *highly* doubt you need a 470uF electrolytic as an input cap for each 7805 for a DAC digital supply. The AKM apps guys might be crazy for all we know, or it covered up some other deficiency. I always look closely at eval boards and schematics and try to gauge the quality to know how closely I should follow it. This one has some weird stuff...

I don't think this component would work, because I need a 15V input, and this component has a 1.9 V to 5.5 V operating input voltage range.

That being said, you are totally correct, I am positively overthinking this whole thing, but this is allowing me to understand what regulators are for, how they work, what their parameters are, etc. All this must be totally obvious to you, but I am really starting from scratch, therefore none of it makes sense to me at first. It's only when trying to solve some puzzles that a picture starts to form. Of course, some of these puzzles are totally pointless at first. But once you've solved a few of them, you can start solving some that are actually useful.

As far as the 470μF capacitors are concerned, I really don't like the fact that they are using so many of them: these are big and expensive. That being said, the 100μF and 220μF have the same footprint, and my primary constraint is PCB real estate, not BoM cost, so I'm not too concerned about them.
 
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I don't think this component would work, because I need a 15V input, and this component has a 1.9 V to 5.5 V operating input voltage range.

That being said, you are totally correct, I am positively overthinking this whole thing, but this is allowing me to understand what regulators are for, how they work, what their parameters are, etc. All this must be totally obvious to you, but I am really starting from scratch, therefore none of it makes sense to me at first. It's only when trying to solve some puzzles that a picture starts to form. Of course, some of these puzzles are totally pointless at first. But once you've solved a few of them, you can start solving some that are actually useful.

Isn't the DAC digital supply 3.3V and 1.8V? Dropping almost 12V across a linear regulator is usually a bad idea. If the DAC draws 100 mA at 3.3V you would dissipate over 1W in the regulator. Even if it was half that worst case, it's still 0.5W which might get warm.

Just use 47uF tantalums if you must go with 7805s, but the high input voltage is costing you in terms of the cap size too. I doubt you need more than 47uF for such a load.

My best advice is something I should take more of myself. Keep it as simple as possible, get something done, and then improve on it iteratively. Trying to achieve perfection in the first attempt is hard. Now, I'm not saying you shouldn't do research, but you might want to prototype some sections in larger areas and get a feel for what you need.
 
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Isn't the DAC digital supply 3.3V and 1.8V? Dropping almost 12V across a linear regulator is usually a bad idea. If the DAC draws 100 mA at 3.3V you would dissipate over 1W in the regulator. Even if it was half that worst case, it's still 0.5W which might get warm.

Just use 47uF tantalums if you must go with 7805s, but the high input voltage is costing you in terms of the cap size too. I doubt you need more than 47uF for such a load.

My best advice is something I should take more of myself. Keep it as simple as possible, get something done, and then improve on it iteratively. Trying to achieve perfection in the first attempt is hard. Now, I'm not saying you shouldn't do research, but you might want to prototype some sections in larger areas and get a feel for what you need.

Well, that's exactly what I am trying to do with these regulator boards:

1. LT3045 REG board
2. LT3045 + LT1963 REG board
3. LT8609A + LT3471 + LT1965 + TPS7A47/TPS7A33 PSU board
4. DAC board
5. USB board

I am not planning to drop 12V. Instead, I am planning to do what is done on the AK4499EQ evaluation board:

- On page 57, using the LT1965 as a replacement for the NJM78M05 to go from +15V MVDD+ down to +5V VDDL/R.
- On page 54, using the LT1965 as a replacement for the NJM78M05 to go from +15V MVDD+ down to +5V AVDD.

Now the question is: what do we do for going from 15V down to 3.3V for TVDD? This is done with a single BA033CC0T on the evaluation board, but I think I'll do it with two LT3045s instead, going from 15V to 5V, then 5V to 3.3V, then using the LT3471 in order to get down to 1.8V.

As far as prototyping in larger areas is concerned, I totally agree with you, but I can't do that before establishing that a smaller design could be achieved with the same components. Therefore, the plan is this:

1. Doing a lot of research upfront.
2. Sketching boards with the target dimensions (small).
3. Prototyping circuits with large evaluation boards.
4. Prototyping circuits with target components.
5. Building the final boards.
6. Iterating until we get something that we like.

I reckon that my process is a bit unusual compared to what is usually done on this forum. This is because I start as a complete newbie with a crazy ambitious project. This might be a bit disconcerting, and I must apologize for all the noise that it might be producing. If it's too much, I'll tone it down. Otherwise, I'll carry on, for I'm getting exactly what I was looking for: an awesome learning experience.
 
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...the high input voltage is costing you in terms of the cap size too.

The high input voltage (+15V) is mandated by the Jung/Didden circuit, but you're right, it does not mean that we have to use it. Instead, since we are planning to have an external PSU giving us +15V, -15V, and +5V, we should start from the +5V supply line. My mistake: I got totally carried away by the schematic, and I forgot that we had this +5V supply line available to us.

In that case the NCP161 would work!

Sorry for my mistake.
 
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The high input voltage (+15V) is mandated by the Jung/Didden circuit, isn't it?

Yeah, I was talking about the digital supplies though.

I guess I'd have to step back and see why you have to go from 15V all the way down if you have some lower voltages already from the PSU board. You could go from the 5V AVDD down probably without an issue (could add a ferrite between the two if you are worried).

I assume LT3471 is a typo for getting the 1.8V though, right? That's a dual output switcher.

Yep, I see you edited and you do have a 5V to use :).
 
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