If you used an external clock divider, it would be used along with 45/49MHz clocks to divide the clock frequency in half for all AK4499 playback modes except for up around 768kHz.
The bad part in all this is that anything you between the clock and the dac chip will add jitter. It is incredibly easy to make jitter worse, and very hard to make it better. Same considerations for an ADC. Maybe it would be worthwhile to make the dac board be able to operate from an internal or external clock. Some very good DAC/ADC's do that. When using playback only, then the local clock to be used to minimize jitter. When recording at the same time the ADC clock would be distributed to the DAC board and wherever else it is needed.
There might be other options too. Depends on the maximum recording sample rate that is supported. The DAC could run on its local clock and use an AK4137 running from the same clock to resample playback during recording. In that case both the DAC and the ADC could use their local clocks. AK4137 can sound pretty good, I used it to good effect in my 2nd modded dac for example. It can also convert PCM to DSD256, which might sound best when using it. Since there is one on the eval board, we could at some point rig it up to test it, something I want to do eventually anyway.
To my way of thinking, one wants whatever sounds best given the constraints of whatever is of overriding importance in a given situation. IMHO, that's the kind of thinking that RME tried to do with ADI-2 (given its target price point) RME: ADI-2
To a large extent, what can be done in that respect is determined by the bottom up part of the design. Good converters require certain constraints in the low-level implementation. Given a particular chip, it depends what it needs around it to sound its best. The problem then becomes how to marry the low level design know-how one has with the top-down product concept the marketing department has convinced management to fund
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I do not think that 768 (also DSD512) is useful to listen the music, unless somebody wants to get DSD256 in DoP
If you used an external clock divider, it would be used along with 45/49MHz clocks to divide the clock frequency in half for all AK4499 playback modes except for up around 768kHz.
The bad part in all this is that anything you between the clock and the dac chip will add jitter. It is incredibly easy to make jitter worse, and very hard to make it better. Same considerations for an ADC. Maybe it would be worthwhile to make the dac board be able to operate from an internal or external clock. Some very good DAC/ADC's do that. When using playback only, then the local clock to be used to minimize jitter. When recording at the same time the ADC clock would be distributed to the DAC board and wherever else it is needed.
There might be other options too. Depends on the maximum recording sample rate that is supported. The DAC could run on its local clock and use an AK4137 running from the same clock to resample playback during recording. In that case both the DAC and the ADC could use their local clocks. AK4137 can sound pretty good, I used it to good effect in my 2nd modded dac for example. It can also convert PCM to DSD256, which might sound best when using it. Since there is one on the eval board, we could at some point rig it up to test it, something I want to do eventually anyway.
To my way of thinking, one wants whatever sounds best given the constraints of whatever is of overriding importance in a given situation. IMHO, that's the kind of thinking that RME tried to do with ADI-2 (given its target price point) RME: ADI-2
To a large extent, what can be done in that respect is determined by the bottom up part of the design. Good converters require certain constraints in the low-level implementation. Given a particular chip, it depends what it needs around it to sound its best. The problem then becomes how to marry the low level design know-how one has with the top-down product concept the marketing department has convinced management to fund
Exactly!
Or are you trying to make me look like the pointy-haired boss in Dilbert?
I really like the idea of having both on-board clocks and external clock input.
I'll try to find a good SMD socket for an external clock.
For SMD RF connectors you might take a look at SMB and MCX types. The latter is a bit smaller, but maybe less common. Both types are snap on, but maybe there is something that just slips on without snapping in place.
Maybe some more at: https://www.rosenberger.com/0_docum...coax/02_Chapter_SMP_Longwipe-SMP_Mini-SMP.pdf
Maybe some more at: https://www.rosenberger.com/0_docum...coax/02_Chapter_SMP_Longwipe-SMP_Mini-SMP.pdf
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I do not think that 768 (also DSD512) is useful to listen the music, unless somebody wants to get DSD256 in DoP
DoP is pretty clever...
VOP or VREF?
If we had some spare room on the DAC board, which power supply circuits should we bring there from the PSU board? VOP for the I-V stage or VREF (the Jung/Didden regulators)? I'm sure it would be best to bring both, but I don't think that we can. But if we could bring just one, which one should it be?
If we had some spare room on the DAC board, which power supply circuits should we bring there from the PSU board? VOP for the I-V stage or VREF (the Jung/Didden regulators)? I'm sure it would be best to bring both, but I don't think that we can. But if we could bring just one, which one should it be?
LDOs for 5v, 3.3v. 1.8v, and the clocks 3.3v (ADM7150 is small, and filter caps can be small SMD ceramic and or tantalum).
So, just to be clear, what you're saying is "neither". Instead, you want the LDOs for the clocks (which was a given), but also for VDD (L1, R1, L2, R2, all 5V), AVDD (5V), TVDD (3.3V), and DVDD (1.8V). Is that correct?
DSDPATH
Does anyone understand why AKM felt the need to provide two separate paths for DSD, one shared with PCM pins and the other shared with pins available only in pin control mode (DEM0, TDM0, TDM1, DCHAIN)?
Since we're going to use Register Mode, the pins used in pin control mode are not available to us. Therefore, should we assume that we'll set DSDPATH to 1 and always use pins 50..54 for DSD while using pins 43..48 for PCM/EXDF?
Or did I miss something?
Does anyone understand why AKM felt the need to provide two separate paths for DSD, one shared with PCM pins and the other shared with pins available only in pin control mode (DEM0, TDM0, TDM1, DCHAIN)?
Since we're going to use Register Mode, the pins used in pin control mode are not available to us. Therefore, should we assume that we'll set DSDPATH to 1 and always use pins 50..54 for DSD while using pins 43..48 for PCM/EXDF?
Or did I miss something?
Question about packages
When two packages are available, like SOIC and SON (for example SOIC-8 and SON-8 for OPA1612, or MSOP-12 and DFN-10 for LT3045), is there any reason why the smaller SON should not be the preferred option, knowing that all the assembly will be done at the fab with reflow? Or is the real estate gain insignificant compared to all the other components that are usually needed (capacitors and resistors), and we're better off with a slightly bigger package?
When two packages are available, like SOIC and SON (for example SOIC-8 and SON-8 for OPA1612, or MSOP-12 and DFN-10 for LT3045), is there any reason why the smaller SON should not be the preferred option, knowing that all the assembly will be done at the fab with reflow? Or is the real estate gain insignificant compared to all the other components that are usually needed (capacitors and resistors), and we're better off with a slightly bigger package?
Question about muting
Mark,
In an earlier post, you mentioned that we might need some additional circuitry on the XLR board in order to prevent some popping noise when switching between PCM and DSD. Why do we need this while the DAC chip has this SMUTE function? And if there is a good reason for adding this circuitry, where could I find an example for it?
Thanks!
Mark,
In an earlier post, you mentioned that we might need some additional circuitry on the XLR board in order to prevent some popping noise when switching between PCM and DSD. Why do we need this while the DAC chip has this SMUTE function? And if there is a good reason for adding this circuitry, where could I find an example for it?
Thanks!
Also, I'm a bit confused about the imperative of mounting these LDO on the DAC board itself. I understand the need to get them as close to whatever they are feeding as possible, but what is good enough? In our current design, the ERM8 connectors are 1 or 2mm from the pins of the DAC chip. Therefore, if we put these LDOs very close to the ERF8 connectors on the PSU board, with 16mm mating height, the LDOs will be about 20mm away from their targets, most of their circuits will be doubled or tripled on the connectors, and the connectors themselves will be shielded. Isn't that good enough?
thermal changes over time can/do cause biases to change internally in circuits. Depending on package/circuit sensitivity, low frequencies can evoke this type of thermal cycling. This is more common in power amps, but I have seen referenced in lower power work as well.
Does this occur in the 1611 in any package? I have not used it yet very much (once) and have no opinions based on personal experience with it.
Cheers
Alan
Got it! I thought Mark had something different in mind. So, this is 100% in the analog domain, no need for some additional digital logic then.
Thanks!
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