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Old 21st July 2019, 10:58 PM   #221
chris719 is online now chris719  United States
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Here you go, another block diagram (Figure 1) that represents how AK4499 and similar parts operate. Note the DAC (and everything after the SAI) is clocked by MCLK.

https://statics.cirrus.com/pubs/appNote/AN306REV1.pdf

This is also your answer to the ESS question, because in a way, the ESS approach with ASRC is very similar to Figure 2 and how the cheap Cirrus and TI DACs that have integrated PLLs to recover the MCLK operate.

Last edited by chris719; 21st July 2019 at 11:01 PM.
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Old 22nd July 2019, 07:50 AM   #222
ishizeno is online now ishizeno
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Default Updated USB and DAC Boards

Here are some updated USB and DAC boards for which the seven regulators (5 NJM78M05 and 2 SMD versions of the BA033CC0T) are mounted directly on the PCB. This will ensure that we do not deviate from the original design of the evaluation board, while reducing the height of the DAC assembly. It will also reduce the BoM of a single DAC board by a cool $90...

The DAC board is certainly a tight fit, and many resistors and capacitors will have to be mounted on the underside. We might also go from 70mm × 35mm to 72mm × 36mm in order to get a tiny bit of extra breathing room. That being said, I really like the layout as it stands.

The isolated part of the USB board has now been broken down into three sections:

1. Oscillators (bottom right with picture in portrait orientation)
2. Outputs (right)
3. Inputs (top)

As a result, the pins located on the top side and used for isolated inputs will not be used by the DAC board, but they could be used by some other boards. This will ensure that we can reuse the USB board across different bricks.

The four balanced outputs on the DAC board are now provided through four separate sets of three pins, which is probably better than two sets of six pins. That being said, their actual positions might evolve a little bit as we finalize the overall component placement.

On the DAC board, we now have 16 pins for the audio inputs and 16 pins for the controls, which will allow us to provide separate ground references for everything we need, but we lost the two extra GPIOs that we had included in an earlier iteration.

Now that we have a high-level validation of the overall design, we will review every single component of the AK4499EQ evaluation board in order to come up with a full BoM. And when that part is done, we will do the same for the USB board.
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Old 22nd July 2019, 10:11 AM   #223
ishizeno is online now ishizeno
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Default Diodes for DAC

Any recommendation for the D300, D301, D302, D303, D320, D321, D322, and D323 diodes of the AK4499EQ evaluation board? Would the DB2132000L used for D1, D2, D3, and D4 be suitable?

Last edited by ishizeno; 22nd July 2019 at 10:19 AM.
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Old 22nd July 2019, 12:37 PM   #224
ishizeno is online now ishizeno
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Default DAC Board BoM

We have listed all the components for the DAC board on its BoM sheet. This leaves us with a few questions:

- What is the maximum voltage for the 180pF C8, C9, C19, C20, C56, C57, C58, and C59 capacitors?
- What is the maximum voltage for the 0.1μF C39, C40, C41, C42, C47, C48, C68, C69, C70, C75, C80, and C81 capacitors?
- Is R1 a 5.1Ω resistor or a 5.1kΩ resistor?
- What is R7?
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Old 22nd July 2019, 08:40 PM   #225
ishizeno is online now ishizeno
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Quote:
Originally Posted by Markw4 View Post
The LT3045 data sheet shows the recommended board layout in the applications section. You should read the entire applications section carefully to make sure you understand the issues.
Mark,

I just finished reading the manual for the DC2491A demo board of the LT3045. The Kelvin connection method using the split capacitor technique is awesome! And the input trace directly above the return path to cancel EMFs is beautiful. I really wish that all components were so precisely documented and supported by such clean reference implementations... It makes me want to use this component just for the sheer beauty of the circuitry involved.

Thanks a lot for the nudge!
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Old 22nd July 2019, 09:18 PM   #226
Markw4 is online now Markw4  United States
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Quote:
Originally Posted by ishizeno View Post
I really wish that all components were so precisely documented and supported by such clean reference implementations... It makes me want to use this component just for the sheer beauty of the circuitry involved.
It is not done for beauty's sake of course. Its just that high performance circuits require careful design in order to minimize errors. If a very high level of performance is of no particular benefit, then no need to waste time and money. Find where the problems are and focus on improving those those things.
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Old 22nd July 2019, 09:24 PM   #227
ishizeno is online now ishizeno
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Quote:
Originally Posted by Markw4 View Post
It is not done for beauty's sake of course. Its just that high performance circuits require careful design in order to minimize errors. If a very high level of performance is of no particular benefit, then no need to waste time and money. Find where the problems are and focus on improving those those things.
For an engineer, these are words of wisdom. But the artist wants to see beyond...
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Old 22nd July 2019, 09:36 PM   #228
Markw4 is online now Markw4  United States
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Originally Posted by ishizeno View Post
But the artist wants to see beyond...
Many artists fail to learn well their chosen craft, and without that vision is unlikely to come to much.
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Old 22nd July 2019, 09:40 PM   #229
ishizeno is online now ishizeno
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Many artists fail to learn well their chosen craft, and without that vision is unlikely to come to much.
Touché ! ;-)
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Old 23rd July 2019, 01:54 AM   #230
5th element is offline 5th element  United Kingdom
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Quote:
Originally Posted by chris719 View Post
I posted a block diagram of a relatively modern delta sigma DAC which shows the switched capacitor DAC clocked directly from MCLK. If anyone's repeating the same thing over and over, it would be you . This isn't a matter of my opinion, the DAC is just clocked by MCLK.
Yes you did. The diagram shows the rates that the various parts of the DAC run at and shows the required clock signals for the final parts of the conversion process. It does not however show explicitly that the MCLK is what dictates the start of the conversion process.

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Originally Posted by chris719 View Post
The reference to start the conversion is MCLK. The actual DAC operates at the oversampled rate that is the output rate of the DSM. I am waiting for your explanation as to how the actual converter can be clocked at Fs or 64*Fs (word and max bit clock rates) when the DAC rate is 128 or 256*Fs.
I've never said that the converter is clocked at fs or whatever. Where you've come up with this idea I do not know as it shows a breakdown in communication. Either you've not understood what I've said or you've not read what I've written.

What I've said is that the high speed operation of the DS DAC requires the MCLK to work but that the LR clock is used as the timing reference that tells the DAC when to convert data.

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Originally Posted by chris719 View Post
I am not sure why you can't see that the clock for the converter can be phase independent of the clocks used to clock the data into the digital filters. There are these structures called registers / buffers, you know. This is all still in the digital domain.
I've said before that I am aware of buffers/input registers, did you choose to ignore this?

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Originally Posted by chris719 View Post
You are right that the MCLK absolute phase isn't important, but it still must be frequency locked. You are reading into that statement and coming up with an incorrect conclusion.
The reason why I can't see the separation of the two is because the exact timing of when each subsequent word should be processed is contained within the rising edges of the LR clock. As there is no phase relationship between the rising edges of the LR clock and the MCLK this exact moment is lost if you were to use the MCLK for timing alone.

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Originally Posted by chris719 View Post
Because ESS uses an ASRC... so there is not an input MCLK accompanying the input stream.
That wasn't the point I was trying to make. The point was that the exact timing of when to process the data is highly important and that without a phase relationship between the LR clock and MCLK you can't simply rely on the MCLK to define this moment.

The ESS paper itself compares the effect of jitter present on the data lines with a standard DS DAC to the effect on the ESS DAC. Obviously the ESS DAC separates the incoming data from the incoming data clock and resamples, so any jitter present on the data lines is irrelevant. But the paper clearly shows that this has a negative effect on a normal DS DAC.


Quote:
Originally Posted by chris719 View Post
Like I said, if this simple yes/no test doesn't do it for you, please start with explaining how the internal DAC can be clocked at a rate higher than the bit clock or word clock if it is clocked by bit clock or word clock as you maintain. If there were an internal PLL or FLL to multiply those clocks, then why would there even need to be an MCLK input?
I am not saying that the internal DAC is clocked by the data clocks.

What I am saying is that the MCLK runs the high speed sections of a DS DAC. But that the LR clock is used as the timing reference for when to start processing the data bytes within the DAC itself. Obviously the conversion isn't instant with a group delay involved from the input to output.

I will read those links later.
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