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Old 21st July 2019, 09:52 AM   #211
5th element is offline 5th element  United Kingdom
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Quote:
Originally Posted by chris719 View Post
You still don't seem to understand this.

First, jitter on bit clock, word clock, and data do NOT matter one iota for AK4499 and similar parts. Your point is just plain wrong. The reason why is very simple and it's already been explained by me and Mark's quote from the datasheet. You only need to understand where the data enters the analog domain and what clock drives that action.

Second, the test by JA is done at the external interface level. The point of this test is to hamper the MCLK recovery of SPDIF receivers. It doesn't apply here.
I understand exactly what you are saying I just don't agree with it. All you've done is repeat the same thing over and over again without actually providing anything to back it up.

What Mark posted was simply repeating what I had said myself a few posts previously and the picture you linked was, again, repeating what I had said myself. That the master clock is required for the operation of the DS DAC. That is it. You won't get any argument from me on this matter, we are in agreement. But so far all you've said is that the master clock is required for the operation of the DS DAC.

Of course the DAC is going to buffer the entire 32 bit word, most likely the 64 bit stereo word, before actually processing it. Again you'll get no argument from me on this either.

What I am saying is that the timing, the reference that is used to start the conversion process and then when to process the subsequent words is tied to the bit clock, LR clock, data line, not the master clock. How can it not be?

The master clock phase isn't relevant to the conversion process at all, the data sheets say as much. The phase of the clock is exactly what would describe when the data should be processed and without it being aligned with the bit clock that information is lost.

The information within the data being fed into the DAC that contains the precise point in time of when the data should be processed isn't tied to the master clock (the rising edges of the bit clock contain this data and there's no phase relationship between the rising edges of the bit clock and master clock, so the master clock can't contain it). Yet the time of when the data should be processed is very relevant to it's conversion, ESS say as much in their white paper. You can't just start the conversion process at some arbitrary rising edge of the master clock.

And if jitter present on the data stream isn't important to the conversion process why do ESS go to such extreme lengths to remove it? And write white papers on the removal of it?

I am not saying that you are wrong mind you, a lot of what you're saying makes sense, but you aren't providing me with any technical documents to back up what you are saying.
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Old 21st July 2019, 11:03 AM   #212
HpW is offline HpW
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Quote:
Originally Posted by ishizeno View Post
which is currently the most powerful chip offered by XMOS (32 cores).
Keep in mind using XMOS, the maximal possible SR speed is limited by a single core. This means, de terminated by a bit stream by I2C to single bin by a single core . In other words, only one core may used for a single HW bin.

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Old 21st July 2019, 12:22 PM   #213
ishizeno is offline ishizeno
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Originally Posted by HpW View Post
Keep in mind using XMOS, the maximal possible SR speed is limited by a single core. This means, de terminated by a bit stream by I2C to single bin by a single core . In other words, only one core may used for a single HW bin.

Hp
Good point!
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Old 21st July 2019, 12:37 PM   #214
ishizeno is offline ishizeno
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Default DAC Board Audio Outputs

We've added the pins for our audio outputs on the pins analysis sheet. As mentioned earlier, everything downstream of the I-V conversion circuits will be placed on the XLR board, including the summing stage for mono mode. As a result, we just need 9 pins for audio outputs (8 signals and one AVSS). Now, I wonder if we should carry one AVSS ground reference per channel (4 pins instead of 1). Any recommendation?
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Old 21st July 2019, 01:46 PM   #215
Markw4 is offline Markw4  United States
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Probably a mistake to decide on using only +20v power now. That would imply you would need a switching supply to produce the -15v best used for some circuitry. Eliminating all switching noise from an ultra low distortion dac output is possible, but non-trivial. So far, I am only aware of Bechmark Media products doing that successfully, and the products in question have selling prices starting above $2,000 per unit. At that price point, and with a lot of engineering effort, SMPS can work for audio. However, most manufacturers have not done as well with it and low cost products have sound quality issues as a result.

Again, I would suggest to get AK4499 eval board working at its best, then try using the prospective power supply with it. After that make a decision if you have the engineering skills to make it work for your project.

ishizeno, I am about a three-hour drive from where you are. Pretty soon, not quite yet, I would be willing to have you come here for part of a day to visit. I could let you see and hear the AK4499 eval board playing high quality DSD512 as well as other formats, and also likely be able to introduce you to Jam, a high-end audio designer friend. If you think you might be interested, we could talk about it some more by offline.

Last edited by Markw4; 21st July 2019 at 01:53 PM.
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Old 21st July 2019, 02:03 PM   #216
ishizeno is offline ishizeno
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Default Updated USB Board Sketch

Here is an updated sketch for the USB board. Following our pin analysis, we've concluded that we had enough space to include some IS and S/PDIF inputs as well. This will allow the board to be used for bricks that expose these inputs, even though our standard DAC bricks will not. In order to make that possible, we went from three to four Si866x low power six-channel digital isolators (marked "DI" on the sketch). Also, we've increased the count of GPIOs from 12 to 14 in order to get 2 spare ones on top of the 12 that are required by the DAC board (better be safe than sorry). And we still have quite a bit of room for the regulator(s), capacitors, and resistors that will need to be installed, even though most of them can go on the board's underside. Most importantly, we made sure to group the GPIOs and IC interface on a single set of headers, while putting all isolated IOs on another set. This will make it easier to connect the USB board to the DAC board. On the sketch, the red line indicates the isolated area.
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File Type: jpg USB.jpg (638.7 KB, 86 views)

Last edited by ishizeno; 21st July 2019 at 02:13 PM.
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Old 21st July 2019, 02:13 PM   #217
ishizeno is offline ishizeno
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Quote:
Originally Posted by Markw4 View Post
Probably a mistake to decide on using only +20v power now. That would imply you would need a switching supply to produce the -15v best used for some circuitry. Eliminating all switching noise from an ultra low distortion dac output is possible, but non-trivial. So far, I am only aware of Bechmark Media products doing that successfully, and the products in question have selling prices starting above $2,000 per unit. At that price point, and with a lot of engineering effort, SMPS can work for audio. However, most manufacturers have not done as well with it and low cost products have sound quality issues as a result.
I did not realize that. The post introducing the OSVA AAPSU01 mentions that the nominal input can be in the 9-20V range, while "the symmetric outputs voltages can be configured to any values between about +/-6V to +/- 15 V." Did I miss something? I must read like the total newbie that I am right now... ;-)

Quote:
Again, I would suggest to get AK4499 eval board working at its best, then try using the prospective power supply with it. After that make a decision if you have the engineering skills to make it work for your project.
Agreed. I can't wait to get my hands (and ears) on one...

Quote:
ishizeno, I am about a three-hour drive from where you are. Pretty soon, not quite yet, I would be willing to have you come here for part of a day to visit. I could let you see and hear the AK4499 eval board playing high quality DSD512 as well as other formats, and also likely be able to introduce you to Jam, a high-end audio designer friend. If you think you might be interested, we could talk about it some more by offline.
I would love that! Thank you so much for the offer. Please contact me at ishi at ishi dot io whenever you want.
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Old 21st July 2019, 06:14 PM   #218
ishizeno is offline ishizeno
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Default Redesigned Stack

We have redesigned our stack in order to align our board-to-board interconnects with the AK4499EQ's pinout. The new design will significantly reduce the lengths of most traces and makes room for a proper power section on the DAC board.

The attacked stack shows how two USB boards and two DAC boards will share a common PSU board. As a reminder, the USB board is 1 1 (35mm 35mm), while the DAC and PSU boards are both 2 1 (70mm 35mm). With that in mind, the stack picture shows how the two DAC boards are laid on top of the PSU board, but rotated by 90 degrees.

The DAC picture shows the redesigned layout for the DAC board, with the power section at the top (including three 470μF capacitors and three regulators that were overlooked in the original design), plus an upcoming 5V to 3.3V regulator.

In order to make room for all this, the AK4499 is lowered a bit, allowing for a perfect alignment with two sets of 12 headers, with control inputs on the West side and audio inputs on the East side. The pin analysis that we conducted earlier today confirms that this is an appropriate layout, at the exception of the MCLK pin, which is on the "wrong" side of the chip (I'm not sure exactly why AKM engineers did this).

The new design still makes room for the LT3045-78XX and provides two sets of 6 headers for the audio outputs, one on the North side and one on the South side, directly adjacent to their related OPA1612 OpAmps.

This "crossgrain" laminate structure of the 5 boards kills two birds with one stone: it helps reduce the length of traces and it provides structural integrity for the assembly, without having to use any screws. Overall, I like it a lot better than the previous design.
Attached Images
File Type: jpg Stack.jpg (976.2 KB, 80 views)
File Type: jpg DAC.jpg (953.6 KB, 80 views)
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Old 21st July 2019, 09:59 PM   #219
chris719 is offline chris719  United States
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Quote:
Originally Posted by Markw4 View Post
Probably a mistake to decide on using only +20v power now. That would imply you would need a switching supply to produce the -15v best used for some circuitry. Eliminating all switching noise from an ultra low distortion dac output is possible, but non-trivial. So far, I am only aware of Bechmark Media products doing that successfully, and the products in question have selling prices starting above $2,000 per unit. At that price point, and with a lot of engineering effort, SMPS can work for audio. However, most manufacturers have not done as well with it and low cost products have sound quality issues as a result.

Again, I would suggest to get AK4499 eval board working at its best, then try using the prospective power supply with it. After that make a decision if you have the engineering skills to make it work for your project.

ishizeno, I am about a three-hour drive from where you are. Pretty soon, not quite yet, I would be willing to have you come here for part of a day to visit. I could let you see and hear the AK4499 eval board playing high quality DSD512 as well as other formats, and also likely be able to introduce you to Jam, a high-end audio designer friend. If you think you might be interested, we could talk about it some more by offline.
I think you can do better with a SMPS than a linear supply in a single box system, actually. Whether everyone can do it properly is a different question. The price of the unit doesn't really have anything to do with the quality of the power supply, only the skill of the designer. Benchmark's parts are garden variety LT buck / boost converters which are only a few dollars each. So, I guess we agree to some extent. I wouldn't automatically rule it out, though.
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Old 21st July 2019, 10:25 PM   #220
chris719 is offline chris719  United States
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Quote:
Originally Posted by 5th element View Post
I understand exactly what you are saying I just don't agree with it. All you've done is repeat the same thing over and over again without actually providing anything to back it up.
I posted a block diagram of a relatively modern delta sigma DAC which shows the switched capacitor DAC clocked directly from MCLK. If anyone's repeating the same thing over and over, it would be you . This isn't a matter of my opinion, the DAC is just clocked by MCLK.

Quote:
Originally Posted by 5th element View Post
What I am saying is that the timing, the reference that is used to start the conversion process and then when to process the subsequent words is tied to the bit clock, LR clock, data line, not the master clock. How can it not be?
The reference to start the conversion is MCLK. The actual DAC operates at the oversampled rate that is the output rate of the DSM. I am waiting for your explanation as to how the actual converter can be clocked at Fs or 64*Fs (word and max bit clock rates) when the DAC rate is 128 or 256*Fs.

I am not sure why you can't see that the clock for the converter can be phase independent of the clocks used to clock the data into the digital filters. There are these structures called registers / buffers, you know. This is all still in the digital domain.

You are right that the MCLK absolute phase isn't important, but it still must be frequency locked. You are reading into that statement and coming up with an incorrect conclusion.

Quote:
Originally Posted by 5th element View Post
And if jitter present on the data stream isn't important to the conversion process why do ESS go to such extreme lengths to remove it? And write white papers on the removal of it?
Because ESS uses an ASRC... so there is not an input MCLK accompanying the input stream.

Quote:
Originally Posted by 5th element View Post
I am not saying that you are wrong mind you, a lot of what you're saying makes sense, but you aren't providing me with any technical documents to back up what you are saying.
This can all be boiled down to one simple yes or no question. Is the actual D->A converter block clocked by MCLK? The datasheet of this AK4499 and several other parts explicitly say Yes. Until the data reaches the point where it is clocked into the analog domain, none of the other clocks are critical and none of the jitter matters unless it is so severe that you violate setup and hold timing. So, you could use the bit clock or word clock to do whatever you want beforehand, but the only clock that matters is the one that puts the data in the analog domain.

Like I said, if this simple yes/no test doesn't do it for you, please start with explaining how the internal DAC can be clocked at a rate higher than the bit clock or word clock if it is clocked by bit clock or word clock as you maintain. If there were an internal PLL or FLL to multiply those clocks, then why would there even need to be an MCLK input?


If you don't want to believe just me:

QuantAsylum QA400 and QA401

Best place for digital isolator

Which is the jitter-sensitive DAC input?

Last edited by chris719; 21st July 2019 at 10:47 PM.
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