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Old 17th July 2019, 03:54 PM   #101
Markw4 is offline Markw4  United States
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Quote:
Originally Posted by ishizeno View Post
If that is the case, what can be done to preserve the output signal between the operational amplifiers mounted on the DAC board and the XLR connector(s) mounted on another board?
Any I/V opamps should be on the same ground plane as the dac chip, according to ESS. http://www.esstech.com/files/4514/40...PCB_Layout.pdf
There can also be a little RF that comes out of a dac chip, which can get into the opamps and affect distortion. Reference designs don't always get everything completely right/optimal, at least at first for a new type of product. Even today there is discussion about eliminating the 'ESS hump' over at ASR, and it seems that it was an ESS distributor who performed some experiments to find a solution, apparently not ESS itself.

The point is that making a very good dac is still not quite something that can be assured on a first iteration. It can be a project in itself that takes time and effort.

Last edited by Markw4; 17th July 2019 at 03:58 PM.
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Old 17th July 2019, 04:03 PM   #102
ishizeno is offline ishizeno
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Of course! I totally assume that our first iteration won't be good at all, but I'm just trying to reduce the number of things that are totally wrong about it. So, I take it that I should keep the opamps on the same board as the DAC chip, right?

Looking at Figure 83. External I-V Conversion Circuit Example (Mono mode) of 019001308-E-00, is it fair to assume that everything to the right of the I-V Conv. Circuits (the section within a dotted line) could go on the XLR output board, while everything within the dotted line would stay on the DAC board?
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Old 17th July 2019, 04:15 PM   #103
Markw4 is offline Markw4  United States
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Originally Posted by ishizeno View Post
...is it fair to assume that everything to the right of the I-V Conv. Circuits (the section within a dotted line) could go on the XLR output board, while everything within the dotted line would stay on the DAC board?
Assuming you can protect the signals from noise sources and maintain clean grounds, that seems like a reasonable thing to try. Depending on how far and or where the signals might run, you might include a small-ish resistor in series with the I/V outputs to provide some isolation from wiring capacitance.
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Old 17th July 2019, 04:17 PM   #104
ishizeno is offline ishizeno
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That makes sense. Thanks!

Looking at AKM's prototype on this article, I am left with one question: if the primary constraint is space (volume) instead of BoM cost, is it better to have as many discrete ultra low noise power supplies as possible (7 in AKM's prototype) with smaller capacitors, or less power supplies using larger capacitors?

Also, is it fair to say that the quality of the power supplies for the ADC board matters more than the quality of the power supplies for the XMOS board?
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Old 17th July 2019, 04:23 PM   #105
Markw4 is offline Markw4  United States
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Quote:
Originally Posted by ishizeno View Post
... is it better to have as many discrete ultra low noise power supplies as possible (7 in AKM's prototype) with smaller capacitors, or less power supplies using larger capacitors?
The eval board can run on +-15v only, however it will sound better with +-15v, +5v, and +3.3v (good to get the digital loads off the +15v rail). They don't have to be super supplies, as there are secondary regulators on the eval board for most things. More or less the same thing is true for Sabre dacs, use local regulators for things that need them, and general purpose power supplies as pre-regulators.

Quote:
Also, is it fair to say that the quality of the power supplies for the ADC board matters more than the quality of the power supplies for the XMOS board?
That might depend a lot on where the clocks are located. For a synchronous design everything should run on the same master clocks. Also, I2S signals coming out of the XMOS chip may lose their square edges pretty quickly due to interconnection capacitance. With some added complication that could be dealt with of course. They signals could be converted to LVDS at the XMOS, then converted back to LVCMOS near the dac, as one possible example. In such a case one might decide there is some benefit from using a 'reclocker' circuit to restore all the signals before going into the dac. Don't know if it matters all that much with AKM so long as setup and hold times are met. [On the other hand, getting a Sabre dac to lock in synchronous mode (DPLL = 0) might be more complicated, not so much because of setup and hold, but maybe because unspecified I2S noise sensitivity and or slow edges could cause issues.]

Last edited by Markw4; 17th July 2019 at 04:36 PM.
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Old 17th July 2019, 04:39 PM   #106
ishizeno is offline ishizeno
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Default DAC Stack

Here is the stack of boards that will be used for the top part of the two-channel DAC brick:

1. 2-layer XLR Left + XLR Right PCB
2. 8-layer DAC Left PCB
3. 8-layer DAC Right PCB
4. 4-layer PSU PCB (15V, +5V, +3.3V)
5. 4-layer XMOS PCB
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Old 17th July 2019, 06:21 PM   #107
ishizeno is offline ishizeno
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Default AK4499 Evaluation Board Rev.0

We just received the AK4499 Evaluation Board Rev.0 document for the AKD4499-B evaluation board. This will allow us to move forward with the design of our DAC brick. And the board includes both a 4-channel section and a mono channel section with the addition block that we want to implement. Yay!

Last edited by ishizeno; 17th July 2019 at 06:27 PM.
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Old 17th July 2019, 06:22 PM   #108
chris719 is offline chris719  United States
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Just out of curiosity, did you get it from the AKM site, or did you have to contact sales?
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Old 17th July 2019, 06:27 PM   #109
chris719 is offline chris719  United States
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Quote:
Originally Posted by 5th element View Post
I wasn't trying to say that it was the same thing as a USB audio endpoint running in async mode. Why do you keep misunderstand and convoluting the points I'm trying to make. The point being that jitter on the bit-clock, LR clock and data line are important to the end performance of the DAC.
You still don't seem to understand this.

First, jitter on bit clock, word clock, and data do NOT matter one iota for AK4499 and similar parts. Your point is just plain wrong. The reason why is very simple and it's already been explained by me and Mark's quote from the datasheet. You only need to understand where the data enters the analog domain and what clock drives that action.

Second, the test by JA is done at the external interface level. The point of this test is to hamper the MCLK recovery of SPDIF receivers. It doesn't apply here.
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Old 17th July 2019, 06:37 PM   #110
chris719 is offline chris719  United States
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Quote:
Originally Posted by ishizeno View Post
That's a tough one... Not sure which way to go. <snip>
I would use the 22/24 clocks as Mark suggests because 768 kHz is useless other than for bragging rights.

I'd also stick with OPA1612 rather than a budget replacement.

For the power supplies, I haven't seen their eval schematic, but I am pretty sure that LT3042 / LT3045 will work and deliver datasheet-level performance. The LT3042 specs are very similar to the dedicated ESS low noise regulator. I am sure Mark will disagree based on subjective criteria which I don't buy into, but you can make your own decision here. It's safest to copy the evaluation board. It feels like AKM copied the ESS approach, who knows if they tested other alternatives.

I would also make sure you put the LDOs on the boards near the loads. The regulators are most effective then.
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