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Dividing the DAC reclock frequency does improve jitter?
Dividing the DAC reclock frequency does improve jitter?
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Old 2nd May 2019, 11:40 AM   #1
ygg-it is offline ygg-it  Italy
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Default Dividing the DAC reclock frequency does improve jitter?

I'm in the decision whether or not to divide the VCXO reclock signal by 2.

If I reclock the DAC digital signals with a lower frequency clock, (by using an "ideal" N divider) from theory the absolute jitter will be the same but phase noise is better (by 6dB per division).

So, in principle, is it better to reclock SCK, DATA and FSYNC digital signal with a "f/2" clock instead of "f" ? (i.e. 5.6MHz, instead of 11.2MHz) ?

Measurements of jitter reduction are exacly the same in the two cases (Jitter J-test), but sound appears just slightly better with the lower re-clock.

Any idea? Thanks!

http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt

Last edited by ygg-it; 2nd May 2019 at 01:38 PM.
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Old 2nd May 2019, 06:33 PM   #2
MarcelvdG is offline MarcelvdG  Netherlands
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I don't believe dividing off the clock will do any good in this case.

The phase noise gets lower in an ideal frequency divider because you have the same amount of time error (jitter) on a longer period time. The phase error is their ratio multiplied by 2 pi radians, so the phase error gets smaller. But in a reclocker, the input frequencies are the output frequencies, no matter whether you divide the clock.

By the way, the 6 dB per division by two rule only applies to close-in phase noise unless you make a very exotic frequency divider, see The Best DAC is no DAC
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Old 3rd May 2019, 06:59 AM   #3
ygg-it is offline ygg-it  Italy
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Quote:
Originally Posted by MarcelvdG View Post
I don't believe dividing off the clock will do any good in this case.
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Hi Marcel, thank you for the reply, I know you are very smart on PLL!

In fact jitter measurements this time tell nothing, as they are the same in both cases.


My doubt comes from that, since I'm reclocking tre different signals (at 2.8MHz, at 44.1KHz, and at the streaming data) with a unique 11.28MHz clock, this frequency could be too fast for at least the 44.1KHz signal.

So I'm thinking that reckloking at 11.28/2 = 5.6MHz the three I2S signals, is much closer to those frequency, and with the same amount of absolute jitter, hence better.

I cannot divide further as the highest frequency to reclock is 2.8MHz, so I need at least twice of it to clock the flip flop.

But 11.28Mhz reclocker is 256x higher than 44.1Khz, and 4x higher than 2.8Mhz. Is it too much fast for its duty?
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Old 4th May 2019, 05:51 AM   #4
MarcelvdG is offline MarcelvdG  Netherlands
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I assume that you reclock your I2S signals with a clean clock that's synchronized to the incoming bit clock, presumably using the PLL that you wrote about in another thread.

As long as the flip-flops can handle it and as long as you can meet set-up and hold time requirements, there is nothing wrong with using a high clock rate. If the input signal would have such large jitter that the edges can shift by almost a complete clock period of the 11.2896 MHz or more, then you would have to use a lower clock rate to ensure that set-up and hold times are met - but you would have noticed it if there were a set-up and hold time issue.
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Old 5th May 2019, 04:49 AM   #5
ygg-it is offline ygg-it  Italy
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Quote:
Originally Posted by MarcelvdG View Post
I assume that you reclock your I2S signals with a clean clock that's synchronized to the incoming bit clock, presumably using the PLL
That is correct Marcel. By recklocking the three I2S signals via filp flops with 11.2MHz or 5.6MHz clean clock works whitout problems.

Now I'm wondering why by using a 11.2 Mhz or 5.6 MHz to reclock, jitter measurements are exacly the same, THD% are exactly the same at 0dB ,-60dB and -80dB, but they sound different!

And, now, I like both way!

With 11.2MHz sound is more open and midforward, the bass is smooth and full; with 5.6Mhz (half recklock frequency) sound is more detailed, clean and bass are tight and soundstage more focused.

It seems theory doesn't help here this time. I'm probably going to make a selector on the panel to change the reclock frequency on the fly...

Last edited by ygg-it; 5th May 2019 at 04:56 AM.
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Old 5th May 2019, 06:28 AM   #6
Bill Coltrane is offline Bill Coltrane  Netherlands
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Quote:
Originally Posted by ygg-it View Post
I'm in the decision whether or not to divide the VCXO reclock signal by 2.

If I reclock the DAC digital signals with a lower frequency clock, (by using an "ideal" N divider) from theory the absolute jitter will be the same but phase noise is better (by 6dB per division).

So, in principle, is it better to reclock SCK, DATA and FSYNC digital signal with a "f/2" clock instead of "f" ? (i.e. 5.6MHz, instead of 11.2MHz) ?

Measurements of jitter reduction are exacly the same in the two cases (Jitter J-test), but sound appears just slightly better with the lower re-clock.

Any idea? Thanks!

http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt
If you divide with a flip flop, you can't change the absolute amount of jitter. This is because the flip flop is directly clocked by the main clock.

You can use a pll to divide the clock, this can improve of worsen the amount of jitter depending on the design of the pll.


On a side note, what protocol did you use to determine the sound quality of the different clock rates?
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Subjective measurements with the proper protocol is the only thing that matters.

Last edited by Bill Coltrane; 5th May 2019 at 06:31 AM.
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Old 6th May 2019, 03:47 AM   #7
ygg-it is offline ygg-it  Italy
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Quote:
Originally Posted by Bill Coltrane View Post
If you divide with a flip flop, you can't change the absolute amount of jitter. This is because the flip flop is directly clocked by the main clock.

You can use a pll to divide the clock, this can improve of worsen the amount of jitter depending on the design of the pll.


On a side note, what protocol did you use to determine the sound quality of the different clock rates?
Correct, I'm using a PLL and it is true that not always it will improve jitter if not correctly implemented.

I know that I should do an AB random select comparative blind test to be correct and scientific, but I cannot implement it now. Usually I cover my machines and ask my son to random switch between A and B. But here it is impossible because I would recognise the two frequencies because they have different but specific PLL locking time and noise signature.

I will take some few extra days to decide. The DAC must be ready by this month.
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Old 6th May 2019, 12:35 PM   #8
lcsaszar is offline lcsaszar  Hungary
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I believe you have to reclock the BCK (=SCK?) only.
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Old 6th May 2019, 02:11 PM   #9
ygg-it is offline ygg-it  Italy
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Quote:
Originally Posted by lcsaszar View Post
I believe you have to reclock the BCK (=SCK?) only.
In principle SCK should be the most important to reclock.

Are you saying that it is "enough" to reclock just SCK, or that could be even worse to reclock also DATA and FSYNC?

Frankly, I didn't test to reclock just SCK...
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Old 6th May 2019, 05:42 PM   #10
Ken Newton is offline Ken Newton  United States
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Quote:
Originally Posted by ygg-it View Post
Now I'm wondering why by using a 11.2 Mhz or 5.6 MHz to reclock, jitter measurements are exacly the same, THD% are exactly the same at 0dB ,-60dB and -80dB, but they sound different!...
When you report that the jitter measurments are the same, is that measurement a single figure representing the total jitter? If it is, then the next question would be; are the jitter spectrum plots identical? If they are not, the difference in sound you hear is probably due to differences in the character of the two jitter spectrums.
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