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Understanding PLL: why PLL design need a frequency divider?
Understanding PLL: why PLL design need a frequency divider?
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Old 5th February 2019, 05:13 AM   #1
ygg-it is offline ygg-it  Italy
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Default Understanding PLL: why PLL design need a frequency divider?

Hello, in reference to the following similar schemes:

1) 1. Jitter suppression and PLL design

2) http://www.audiocostruzioni.com/a_d/...aniele/PLL.jpg

can you please explain to me why the phase detector (two flip flops and a nand port) should work with a 1:16 frequency divider (11.289MHz / 16 = 705KHz) of the input frequency, instead of working just comparing the two entire input frequencies (MCK and VCXO, both at 11.2896MHz) ?

In simple words what happen if I would use 1:1 (no divider), or 1:2 or 1:4 or even 1:32 frequency dividers?
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Old 5th February 2019, 05:58 AM   #2
abraxalito is offline abraxalito  United Kingdom
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You only need the frequency divider if you want the output clock to run faster than the input i.e. you want a frequency multiplier. If you run at 11.2896MHz input frequency and only want that frequency for output then you've no need for a divider.
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Old 5th February 2019, 07:59 AM   #3
ygg-it is offline ygg-it  Italy
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Quote:
Originally Posted by abraxalito View Post
You only need the frequency divider if you want the output clock to run faster than the input i.e. you want a frequency multiplier. If you run at 11.2896MHz input frequency and only want that frequency for output then you've no need for a divider.
That was what I thought too, but it is not the case: in the above examples both input and output frequencies are the same (11.2896), but the PLL works at 1:16
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Old 5th February 2019, 08:17 AM   #4
abraxalito is offline abraxalito  United Kingdom
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That's not how I read the first link - here are some quotes :
Quote:
For our design we chose to use the sample word buffer: Having the PLL in phase-lock on the word clock (44.1 kHz), does not require longer buffer queues. Operating the PLL on the input bit-clock (32 bits x 2 samples x44.1 kHz = 2.8224 MHz) would have been another usefull option but would leave a small phase (timing) margin for the very slow changing oscillator frequency........This allows easy cooperation with an external PLL locking on the word clock.
Later, when describing the filter that comes after the phase detector, we read :

Quote:
As the actual input signal is a 705kHz digital signal with lots of higher harmonics, these AC components are significantly damped before reaching the opamp.
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Old 5th February 2019, 02:34 PM   #5
ygg-it is offline ygg-it  Italy
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Sorry, but still not clear.

I cannot explain the use of U11 and U12 in the following:

http://members.chello.nl/~m.heijlige...ml/dig_r2c.pdf

Do you?
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Old 5th February 2019, 09:41 PM   #6
MarcelvdG is offline MarcelvdG  Netherlands
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I don't know whether this has anything to do with it, but if the input signal has very severe jitter, like the worst-case test signals specified in the S/PDIF standard, it might run out of the linear region of a normal phase-frequency detector. A divider could solve that.
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Old 6th February 2019, 02:04 AM   #7
abraxalito is offline abraxalito  United Kingdom
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Quote:
Originally Posted by ygg-it View Post
I cannot explain the use of U11 and U12 in the following:

http://members.chello.nl/~m.heijlige...ml/dig_r2c.pdf
They're divide-by-16 counters so that the phase detector's working at 705.6kHz, not 11.2896MHz. Entirely consistent with the text where it says :

Quote:
In our design the PLL operates on a 16x divided master clock frequency, or 11.289MHz / 16 = 705 kHz.
To return to my original comment (post #2) - the divider's present because their PLL is working at 705.6kHz, not at 11.2896MHz. Its a frequency multiplier.
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Old 6th February 2019, 02:47 AM   #8
ygg-it is offline ygg-it  Italy
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Quote:
Originally Posted by abraxalito View Post
their PLL is working at 705.6kHz, not at 11.2896MHz. Its a frequency multiplier.
That is clear, thanks. Why in your opinion they choose to work at 705.6k and not at 11.2896M saving two chips? Why 705.6k and not at 1.4112M or 2.8224M or higher? More stability? More precision? Lower cut-off LPF?
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Old 6th February 2019, 03:16 AM   #9
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From reading the link I got the impression the reason they run at a much lower frequency is the same one @MarcelvdG mentioned - they want to deal with the possibility of more than +/-44nS of jitter. Here's what they say about not operating at 2.82MHz :
Quote:
For our design we chose to use the sample word buffer: Having the PLL in phase-lock on the word clock (44.1 kHz), does not require longer buffer queues. Operating the PLL on the input bit-clock (32 bits x 2 samples x44.1 kHz = 2.8224 MHz) would have been another usefull option but would leave a small phase (timing) margin for the very slow changing oscillator frequency. Furthermore we wanted to make a truly high-quality design with relatively few components. It appeared that the Nippon `SM5842AP' could not only provide high audio quality filtering (such as 32-bit accuracy mathematics), but also provided the option of operating on a dual clock with an internal word buffer. It has a relatively small input circuit section operating on the 'dirty' input clock, a word buffer, and then the data processing and output on a second 'clean' clock. Its datasheet specifies a maximum allowable 3/8 period difference between both clocks. This allows easy cooperation with an external PLL locking on the word clock.
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Old 11th February 2019, 06:07 AM   #10
ygg-it is offline ygg-it  Italy
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Hello, I've finally built PLL designed by Marc Heijligers and team (Guido Tent etc..) with success and with great “technical” satisfaction for me.
I say “technical” as the sonic and measured jitter improvements (see pics, a tiny -5dB jitter improvement) are subtle and the benefit-cost ratio to build this (a synchronous separate PLL clock instead of using the direct receiver MCK clock signal) is unfavourable.

Said this, I've done also few improvements:

1) using 74AS (134 MHz) instead of 74HC (29 MHz)

2) using AD8411 as a ultra fast 4ns clock shaper

3) adopting LT1963 low noise LD voltage regulator plus BC550C low noise transistor

4) inserting a 3-24ns RC delay network in reset path (470R+ 6pF_to_50pF trimmer capacitor) plus a series of NAND gates, to make an effective way to eliminate the dead zone: the shorter the RESET delay in the PFD, the less likely that the PFD will output an incorrect decision. However, we need the RESET delay to be long enough to eliminate the DEAD-ZONE in the PFD. Thus the orange trimmer in the pic. But how to trim this?? I'm trying by randomise tempts but I feel it is unsatisfying. I've done lowering a little the harmonics on the Jitter test signal.

5) choose a higher PLL working frequency. See below

NOW THE BIG ORIGINAL QUESTION: choose the PLL working frequency (WFQ). Original scheme divides both VCXO and MCK by 16 to make the PLL working at 705.6kHZ. I've tried at :16, :8, :4 and :2. All work locking the PLL!

Few considerations of mine:

a) a lower WFQ makes the locking longer; at higher WFQ the PLL lock faster

b) I suppose that 74AS74 shorter propagation delay (vs original 74HC) allows to use higher WFQ

c) very difficult decision to choose the right WFQ, as I didn't fully understand the pro and cons

d) by ear, the :8 (1.4112MHz) and the :4 (2.8224MHz) WFQ sound slight better (but benefits are almost undetectable)

e) with a network player SPDIF input, all the mentioned WFQ work good. But with a CD player SPDIF input, the PLL get randomly unlocks for an instant after some minutes (!!!) with the usual annoying pop and clicks when using the lowest original WFQ (:16 i.e. 705.6kHZ). By using a faster WFQ (:8 i.e. 1.4112MHz and up), both the machines never unlock. Hence, the decision is to skip the original design lower WFQ (:16 i.e. 705.6kHZ).

f) I think that by using a lower WFQ, the PLL less - or slowly- interferes with the VCXO once locked, and this should have a benefit in term of output jitter if the VCXO is clean and well designed

Thus, I'm actually using :8 (1.4112MHz), but I would be happier if someone could kindly explain to me the pro and cons to use a faster or lower WFQ.
Attached Images
File Type: jpg 20190210_174820rid.jpg (599.2 KB, 79 views)
File Type: jpg 20190210_174838rid.jpg (598.5 KB, 80 views)
File Type: jpg Jitter with PLL.jpg (236.2 KB, 79 views)
File Type: jpg Jitter without PLL (MCK direct).jpg (234.2 KB, 75 views)

Last edited by ygg-it; 11th February 2019 at 06:14 AM.
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