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AK4493 DAC
AK4493 DAC
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Old 21st April 2020, 06:51 PM   #81
hidjedewitje is offline hidjedewitje  Netherlands
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Location: The Netherlands
Quote:
Originally Posted by Dimdim View Post
Hi again,
I was currently looking at your SPDIF/AES receiver on your blog.
S/PDIF Receiver with the WM8805 | Dimdim's Blog

And I was wondering why you use 110R and 0.1uF in series and why you only do it for one end of the balanced signal. Shouldn't the impedances be balanced?
If they are not balanced the common mode will turn into differential mode and the whole point of balanced would be gone.
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Old 21st April 2020, 09:56 PM   #82
Dimdim is offline Dimdim  Greece
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Good eye!

Not only is there only a single 0.1u cap in series with Pin 2 when there should also be a second one in series with Pin 3, but the 110R resistor is connected across Pin 2 and GND where it should have been connected across Pin 2 and Pin 3.

These issues were noticed during the actual build, but since I didn't have any s/pdif sources with XLR connections, I didn't bother to fix them, and eventually they were forgotten.

Oh, and one more thing. Officially the WM8805 doesn't even support AES3 at all.

I really prefer the AK4118 to the WM8805. Much easier to control too.
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Old 21st April 2020, 10:27 PM   #83
potstip is offline potstip  Turkey
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Hello,

All the individual design around here on attachments using seperated regulators for power lines. But official one only use seperated reg for vrefhl/r.

But as i directly copied from datasheet here below, my english is far from native.

What i understand here below it ask for seperate lines not seperated regulators. They shared same ground plane.
__________________________________________________ ________
Power lines of VDDL/R should be distributed separately, from the point with low impedance of regulators or other parts.

Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately with low impedance of regulators, etc. maintained.

AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane
__________________________________________________ ________

Help me please if i miss something here? it is regulated voltage at the end. What could be wrong using same regulator?
Attached Files
File Type: pdf dimdim.pdf (584.1 KB, 35 views)
File Type: pdf nihtila.pdf (187.0 KB, 20 views)
File Type: pdf russian.pdf (374.8 KB, 29 views)
File Type: pdf official.pdf (542.3 KB, 22 views)
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Old 22nd April 2020, 06:16 AM   #84
hidjedewitje is offline hidjedewitje  Netherlands
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Join Date: Jan 2016
Location: The Netherlands
Quote:
Originally Posted by Dimdim View Post
Good eye!

Not only is there only a single 0.1u cap in series with Pin 2 when there should also be a second one in series with Pin 3, but the 110R resistor is connected across Pin 2 and GND where it should have been connected across Pin 2 and Pin 3.

These issues were noticed during the actual build, but since I didn't have any s/pdif sources with XLR connections, I didn't bother to fix them, and eventually they were forgotten.

Oh, and one more thing. Officially the WM8805 doesn't even support AES3 at all.

I really prefer the AK4118 to the WM8805. Much easier to control too.
I am going to use the AK4118, but it only has SPDIF in. I would have to make a differential line receiver and you already had a great one. I just couldn't really understand the design choices there, but now I do
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Old 23rd April 2020, 03:17 PM   #85
hidjedewitje is offline hidjedewitje  Netherlands
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Quote:
Originally Posted by potstip View Post
Hello,

All the individual design around here on attachments using seperated regulators for power lines. But official one only use seperated reg for vrefhl/r.

But as i directly copied from datasheet here below, my english is far from native.

What i understand here below it ask for seperate lines not seperated regulators. They shared same ground plane.
__________________________________________________ ________
Power lines of VDDL/R should be distributed separately, from the point with low impedance of regulators or other parts.

Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately with low impedance of regulators, etc. maintained.

AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane
__________________________________________________ ________

Help me please if i miss something here? it is regulated voltage at the end. What could be wrong using same regulator?

It is recommended to use a seperate power supply for digital and analog to prevent common impedance coupling. Sure the decoupling capacitors are possible ferrites decouple from digital noise, but seperate regulators are much more effective. We don't want switching noise in our beloved audio now do we

The datasheet might state differently. It implies that it DOES work if you don't use seperate powersupplies, but that doesn't mean it's the best solution.
Nihtila has done quite extensive research on various voltage regulators. I recommend reading his research on his website.

A shared groundplane is ALWAYS recommended. Don't split it like AKM recommends. Splitting the groundplane only causes more problems than it solves (creating dipole antenna's, increasing current loops). If you want to properly prevent common impedance coupling you should try to suppress the RF current (because the groundplane is mostly inductive, switching CURRENTS are the biggest problems). This can be done by placing ferrite beads in the decoupling circuitry and series resistances in the digital datalines (~47-100 Ohms).
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Old 23rd April 2020, 07:46 PM   #86
potstip is offline potstip  Turkey
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Quote:
Originally Posted by hidjedewitje View Post
It is recommended to use a seperate power supply for digital and analog to prevent common impedance coupling. Sure the decoupling capacitors are possible ferrites decouple from digital noise, but seperate regulators are much more effective. We don't want switching noise in our beloved audio now do we

The datasheet might state differently. It implies that it DOES work if you don't use seperate powersupplies, but that doesn't mean it's the best solution.
Nihtila has done quite extensive research on various voltage regulators. I recommend reading his research on his website.

A shared groundplane is ALWAYS recommended. Don't split it like AKM recommends. Splitting the groundplane only causes more problems than it solves (creating dipole antenna's, increasing current loops). If you want to properly prevent common impedance coupling you should try to suppress the RF current (because the groundplane is mostly inductive, switching CURRENTS are the biggest problems). This can be done by placing ferrite beads in the decoupling circuitry and series resistances in the digital datalines (~47-100 Ohms).
thx for explanation.
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Old 27th April 2020, 06:16 AM   #87
nihtila is offline nihtila  Finland
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Easiest way is probably to use separate regulators at least for VREFL, VREFR, VDDL, and VDDR. From my experience you can share one for DVDD and AVDD. Although if you're spending quite some money on analog regs already, splitting these won't cost much extra.

I shared a regulator between VREFL/VDDL, and another with VREFR/VDDR, one reason being small form factor as one of design goals. That probably caused me lots of 'issues' (not really issues but difficulties ironing out the best performance) I faced later on.

Note that schematics is just one part of the whole thing. Layout is crucial and determines your performance at the end. Your common power impedance etc will depend on the layout. And without measuring you are really just guessing what affects what and how much.
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Old 16th May 2020, 10:07 AM   #88
hidjedewitje is offline hidjedewitje  Netherlands
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Has anyone seen the measurements of the new RME ADI DAC 2 PRO FS?
It uses the AK4493 as DAC, but the performance exceeds the datasheet by a long shot!
2nd and 3rd harmonic at about -130dB!
I noticed that you could exceed the datasheet values based of Nihtila's research, but this isn't a small margin of a hand full of dB's. This is almost 20dB!

I wonder what their implementation looks like.

RME ADI-2 FS Version 2 DAC and Headphone Amp Review | Audio Science Review (ASR) Forum
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Old 16th May 2020, 11:27 AM   #89
hidjedewitje is offline hidjedewitje  Netherlands
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Click the image to open in full size.
There's an image of the PCB layout.
Looks like they use a ceramic, film and large electrolytic for decoupling.

The output stage looks like a multiple feedback filter. The opamps they used are 2 in one package. I assume it's a 2 stage with global feedback. Very nice design overal.
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Old 18th May 2020, 07:42 AM   #90
nihtila is offline nihtila  Finland
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Quote:
Originally Posted by hidjedewitje View Post
Has anyone seen the measurements of the new RME ADI DAC 2 PRO FS?
It uses the AK4493 as DAC, but the performance exceeds the datasheet by a long shot!
2nd and 3rd harmonic at about -130dB!
I noticed that you could exceed the datasheet values based of Nihtila's research, but this isn't a small margin of a hand full of dB's. This is almost 20dB!

I wonder what their implementation looks like.

RME ADI-2 FS Version 2 DAC and Headphone Amp Review | Audio Science Review (ASR) Forum
Archimago (Archimago's Musings) uses the ADC/DAC version for measurements, apparently the ADC in that is great as well.

That distortion is extremely low. May be a particularly good unit as well, of course. I wonder if big elco helps in THD even if not in THD+N. Maybe I should revise some tests as I used THD+N as figure of merit in these and didn't check THD only that often. LT3042 just didn't always seem to like big capacitance at the output but maybe it would be ok.

A few notes on your comparisons though. Datasheet does not give THD but THD+N so it's not 20dB better than DS. THD+N is -115dB which is the same I measure. This is not 0dBFS level yet though and it gets even lower (-117dB) after that in the RME. But often you get better results with higher level. I (and some others) have a knee before 0dBFS so optimal level is slightly lower, here it's also not clear knee although there is a small drop in SINAD at one point.

Nevertheless, excellent results. Seems they have great implementations. In the ADC/DAC one the PCB was I think 10 layers so that pleases engineer as well. Btw, I wonder if they do something in the FPGA and in what mode the DAC is used in.
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