Invert "sdata" from pin 26 of CS8412

[ygg-it]

Hi, what does it happen if I negate (invert) "sdata" from pin 26 of CS8412 to DAC?

I'm using CS8412 in Mode 5 (5 - Out, L/R, 16 Bits LSBJ) with PCM56.

I'm asking this because by inverting SDATA, J-test Jitter is much better, but I'm worrying to have lost the LSB. Or not?

I also prefer the sound by inverting SDATA, but no scheme is inverting it. So, what's happening?

Simulation unfortunately this time doesn’t help.

 

[Ken Newton]

Hi, what does it happen if I negate (invert) "sdata" from pin 26 of CS8412 to DAC?

I'm using CS8412 in Mode 5 (5 - Out, L/R, 16 Bits LSBJ) with PCM56.

I'm asking this because by inverting SDATA, J-test Jitter is much better, but I'm worrying to have lost the LSB. Or not?

I also prefer the sound by inverting SDATA, but no scheme is inverting it. So, what's happening?

Simulation unfortunately this time doesn’t help.

Performing a simple logic inversion of the sdata stream will produce a DAC chip analog waveform phase inversion plus an 1 LSB D.C. offset. I can't offer a ready guess for why a jitter test should be significantly affected.

 

[batteryman]

Performing a simple logic inversion of the sdata stream will produce a DAC chip analog waveform phase inversion plus an 1 LSB D.C. offset. I can't offer a ready guess for why a jitter test should be significantly affected.

If the jitter measurement includes what the LSB is doing, when the data is inverted, the LSB doesn't change (or as often) so the jitter will appear reduced?

 

[Ken Newton]

If the jitter measurement includes what the LSB is doing, when the data is inverted, the LSB doesn't change (or as often) so the jitter will appear reduced?

That sounds plausible. I seem to recall that a J-test toggles the LSB at something like a 229Hz rate to generate close-in jitter sidebands.

Now that I think about it a little more, the digital bipolar zero crossing would be dramatically affected. The digital bipolar zero crossing produces the greatest change of bit states for many multi-bit quantizer type DACs (R-2R, etc.) and so, produces the greatest jitter. Hence the LSB toggling of the J-test, I suppose.

 

[rfbrw]

Nothing happens. It just gets inverted.

 

[Ken Newton]

Nothing happens. It just gets inverted.

Correct only if it is a true 2's complement data inversion, which requires an binary adder unit. A simple logic inversion of the data will leave a 1 LSB offset.

 

[rfbrw]

There is no offset. A one becomes zero and a zero becomes one.

 

[Ken Newton]

There is no offset. A one becomes zero and a zero becomes one.

[sigh]

 

[rfbrw]

Fascinating. You really do think you are right.

 

[ygg-it]

I'm lost.

Are you saying that since J-test has a square wave modulation just on LSB, we are going to affect this test, or even to nullify its modulation effect?

But in reality Jiitter is not improved at all?

 

[ygg-it]

found same discussion...mmm interesting...

'Chibi' phase inverting mod.

 

[rfbrw]

Not the dame thing

 

[MarcelvdG]

There is no offset. A one becomes zero and a zero becomes one.

When you invert 16-bit two's complement data:

1111111111111110 (two's complement for -2) becomes 0000000000000001 (two's complement for +1)
1111111111111111 (two's complement for -1) becomes 0000000000000000 (two's complement for 0)
0000000000000000 (two's complement for 0) becomes 1111111111111111 (two's complement for -1)
0000000000000001 (two's complement for +1) becomes 1111111111111110 (two's complement for -2)

and so on. So clearly there is a sign inversion and a -1 LSB offset.

The number of switching bits stays exactly the same though, so I have no idea why this should affect a jitter measurement.

 

[rfbrw]

So clearly there is a sign inversion

Guess that would be the inverter.

and a -1 LSB offset.

At least you haven't called it dc.

 

[DF96]

Although it is in fact DC. The outcome is a constant -1 LSB from what it should be. That looks very much like DC to me.

 

[rfbrw]

Next time I use an inverter, I'll keep an eye out for this DC signal. The way you all go on about it, it should be pretty hard to miss.

 

[DF96]

-1 at LSB would be quite easy to miss. The reason we "go on about it" is that someone was denying it.

 

[rfbrw]

Run the output of a NCO through a pair of dacs inverting the input to one. All you will see is a waveform and its mirror image but bipolar zero for the inverted waveform displaced by 1 lsb. How you get a constant value from a single varying value is beyond me.

 

[abraxalito]

That 'displaced by 1lsb' is indeed a DC offset.

 

[rfbrw]

There is no DC to be measured. The displacement is only relative. In absolute terms there is only the waveform just inverted.