Just brainstorming
Just brainstorming:
Thanks to all your inputs I think now that there must be a correlation with a j-test (attached a fraction of what I'm using) and playing with LSB by inverting sdata. I suspect that I'm masking the test in some way, hence the test loses its efficacy when inverting sdata due to the LSB offset.
Also because by inverting sdata, I'm using extra 74As logic, thus Jitter should be greater, not reduced!
I read:
The J-test signal creates a jitter “torture test” at exactly 1/4 the sampling rate combined with toggling the lowest bit in a way that exposes jitter.The signal has two components, the first being a square wave with a period of 4 samples. On conversion to analog at a sample rate of 44.1 kHz this signal would produce a sine wave with an amplitude of–3.01 dB FS at 11.025 kHz. This is added to the second component, a square wave of amplitude 1 LSB.This square wave is repeated at a low frequency.
Looking at 16 bit wave file with an hexadecimal editor: a repetitive transitions from “C000 C000 4000 4000” to “BFFF BFFF 3FFF 3FFF”.
I don't know what is happening to “C000 4000 BFFF 3FFF” at the output of CS8412 but suppose that:
C000 = 49152 - 32768 = + 16384 = 0100000000000000 in two's complement
4000 = 16384 - 32768 = - 16384 = 1100000000000000 in two's complement
BFFF = 49151 - 32768 = + 16383 = 0011111111111111 in two's complement
3FFF = 16383 - 32768 = - 16385 = 1011111111111111 in two's complement
Now if we invert them, sequence will become:
1011111111111111= 3FFF
0011111111111111= BFFF
1100000000000000= 4000
0100000000000000= C000
which looks sequentially different (inverted) and could not innest jitter at all, or innest a different value of jitter.
What do you think?
Just brainstorming:
Thanks to all your inputs I think now that there must be a correlation with a j-test (attached a fraction of what I'm using) and playing with LSB by inverting sdata. I suspect that I'm masking the test in some way, hence the test loses its efficacy when inverting sdata due to the LSB offset.
Also because by inverting sdata, I'm using extra 74As logic, thus Jitter should be greater, not reduced!
I read:
The J-test signal creates a jitter “torture test” at exactly 1/4 the sampling rate combined with toggling the lowest bit in a way that exposes jitter.The signal has two components, the first being a square wave with a period of 4 samples. On conversion to analog at a sample rate of 44.1 kHz this signal would produce a sine wave with an amplitude of–3.01 dB FS at 11.025 kHz. This is added to the second component, a square wave of amplitude 1 LSB.This square wave is repeated at a low frequency.
Looking at 16 bit wave file with an hexadecimal editor: a repetitive transitions from “C000 C000 4000 4000” to “BFFF BFFF 3FFF 3FFF”.
I don't know what is happening to “C000 4000 BFFF 3FFF” at the output of CS8412 but suppose that:
C000 = 49152 - 32768 = + 16384 = 0100000000000000 in two's complement
4000 = 16384 - 32768 = - 16384 = 1100000000000000 in two's complement
BFFF = 49151 - 32768 = + 16383 = 0011111111111111 in two's complement
3FFF = 16383 - 32768 = - 16385 = 1011111111111111 in two's complement
Now if we invert them, sequence will become:
1011111111111111= 3FFF
0011111111111111= BFFF
1100000000000000= 4000
0100000000000000= C000
which looks sequentially different (inverted) and could not innest jitter at all, or innest a different value of jitter.
What do you think?
