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16x Digital interpolation filter - drive PCM56, PCM58, AD1865 and so on up to 768 kHz
16x Digital interpolation filter - drive PCM56, PCM58, AD1865 and so on up to 768 kHz
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Old 5th September 2018, 12:33 PM   #1
3lite is offline 3lite  Poland
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Default 16x Digital interpolation filter - drive PCM56, PCM58, AD1865 and so on up to 768 kHz

Hello

In the last month I've been working on a custom digital interpolation FIR filter implemented on an FPGA (Spartan-6 XC6SLX9). This filter does pretty much the same thing as well known DF1706, SM5847, PMD100, and so on. However, its ability to reconstruct and attenuate a signal is way beyond those

The filter contains 8192 coefficients and it interpolates the data by a factor of 16 times (e.g. 44.1 kHz to 705.6 kHz and 48 kHz to 768 kHz). It has several FIFOs built in since its core is running asynchrounsly (at 225 MHz) while the MCLK is used only to clock data out of FIFO and to create LE (latch enable) signal for the DAC.
In fact, this filter does always interpolate to 705.6 kHz and 768 kHz (an integer factor of the input) and accepts data up to 768 kHz / 32 bits. In order to do that it works like a sample rate converter, so it interpolates and decimates at the same time. However, it should be noted that for 44.1 kHz and 48 kHz it does not decimate at all, but for anything higher than 44.1 kHz and 48 kHz it still interpolates data 16 times, so e.g. having 96 kHz input means that the data is interpolated up to 1536 kHz, but decimated back to 768 kHz. The same goes to 768 kHz input which is interpolated to 12.288 MHz (in a mathematical sense of course) and decimated back to 768 kHz.

It should be noted that along with huge amount of coefficients (8192) this filter incorporates multiply-accumulate units of 32x35 bits wide. It means that the input data word is fully accepted up to 32 bits (without any truncation for that matter) and coefficients are quantized on 35 bits resulting in unmatchable accuracy of the math it does to calculate the output sample

In the title of this thread I did mention you can drive PCM56, PCM58, PCM63, AD1862, AD1865 and so on up to 768 kHz. How is that possible? The filter contains a self reconfiguratable oscillator which sets its frequency depending on the output length (16, 18, 20 or 24 bits). It means that the output bit clock (CLK) is running fully asynchronously from the LE (latch enable) signal which is generated by dividing the provided MCLK signal, so data is latched in almost all DACs without any extra jitter introduced by the oscillator itself. In fact, the filter contains 3 sets of FIFOs (6 FIFOs for both channels) - one in its input (I2S) before going to the core, another one on the core output and the last one for the final oscillator to clock data into the DAC. Besides all of that this technique introduces a quiet zone after the latch signal going down, so it should give DAC some time to settle down with its output before clocking in another sample

Depending on the word length the following frequencies are created on the CLK output:

16 bits - 14 MHz
18 bits - 15.5 MHz
20 bits - 17 MHz
24 bits - 20 MHz

It means that certain DACs such as PCM56 and AD1865 will be running at the edge with 768 kHz stream, but they will work just fine according to my tests. The LE (latch enable) signal is always 705.6 kHz or 768 kHz depending on the input (either multiply of 44.1 kHz or 48 kHz).

0 dBFS @ 20 kHz:

Click the image to open in full size.

-60 dBFS @ 1 kHz:

Click the image to open in full size.

Jitter test @ 48 kHz with LSB toggled @ 250 Hz:

Click the image to open in full size.

Filter attenuation (linear phase) - white noise @ 48 kHz:

Click the image to open in full size.

All measurements were performed using PCM58.

The filter has I2S input with signals of MCLK, BCLK, LRCK and DATA. However, MCLK can be fed by the same source as BCLK signal (if no MCLK is available) assuming that BCLK has a rate of 32x, 64x, 96x, 128x Fs or similar since the filter has to determine its frequency to know how to divide it in order to create LE (latch enable) signal. Any exotic values of BCLK rate will not work as MCLK, so keep that in mind. The jitter and synchronization of FIFOs depends purely on the MCLK signal, so in the long term it needs to be synchronous with LRCK (in almost all cases it is, since BCLK and LRCK should be derived from a divided MCLK clock).

Following frequencies are supported as MCLK:

49.152 MHz
45.1584 MHz
36.864 MHz *
33.8688 MHz *
24.576 MHz
22.5792 MHz
18.432 MHz *
16.9344 MHz *
12.288 MHz
11.2896 MHz
9.2160 MHz *
8.4672 MHz *
6.144 MHz
5.6448 MHz
4.608 MHz *
4.2336 MHz *
3.072 MHz
2.8224 MHz
1.536 MHz
1.4112 MHz

Those with asterisk are usually used in CD-Players and it should be possible to use the filter within a CD-Player once input is attenuated using 170 Ohm or so resistor per line (in order not to damage the FPGA and its I/O pins due to 5V logic levels). The filter can be powered by an external supply (5V or higher) or by providing a direct 3.3V power supply (it is up the user).

Following outputs are provided by the filter:

CLK - clock for data
LE - latch enable signal
SD_L - serial data for the left channel (and its inversion with the line above it, so you can create a differential DAC for XLR outputs)
SD_R - serial data for the right channel (and its inversion with the line above it, so you can create a differential DAC for XLR outputs)
3.3V - main power supply
GND - ground

It should be noted that the filter does have a TDPF (triangular probability density function) dithering algorithm as well. It can be turned on or off by a jumper depending on your preferences.

The price for a fully assembled and ready to use board will be 125 EUR.

Final revision of 16x interpolation version:

Click the image to open in full size.

Click the image to open in full size.

ROM jumper decides which type of filter should be loaded during boot process. There are two filters available, one is linear phase and the other one is a minimum phase Both of them have 8192 taps.

Besides that yesterday I did finish a special version of this filter for TDA1540 / TDA1541 on a bit changed PCB with 8x interpolation (maximum input stream up to 384 kHz). It has a synchronous CLK signal and offset binary format along with LE signal acting as a "strobe" after clocking in all bits. I did test it with a TDA1541A and it works like a charm. The only limitation with that version is the actual requirement of MCLK (since CLK is synchronous and it is derived from the MCLK itself). Following MCLK rates are supported: 49.152 MHz, 45.1584 MHz, 36.864 MHz, 33.8688 MHz, 24.576 MHz, 22.5792 MHz, 12.288 MHz and 11.2896 MHz.

The filter can be directly powered by an external USB to I2S converter, but it draws about 300 mA of extra current, so keep that in mind. Also, it is a 4-layer PCB. Dimensions are 50 mm x 47 mm.

This thread is for a technical discussion only and to check whether there is an interest in such project. Anyway, if there are any questions feel free to ask

Last edited by 3lite; 1st November 2018 at 12:29 PM.
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Old 5th September 2018, 03:21 PM   #2
mlloyd1 is offline mlloyd1  United States
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16x Digital interpolation filter - drive PCM56, PCM58, AD1865 and so on up to 768 kHz
ahem....
there is some interest here.

mlloyd1
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Old 5th September 2018, 04:03 PM   #3
Alexandre is offline Alexandre
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A very interesting development!
-Alex
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Old 5th September 2018, 04:37 PM   #4
batteryman is offline batteryman  United Kingdom
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Very impressive. I would not know where to start designing something this sophisticated but I prefer the sound of NOS balanced TDA1541 and AD1865. (just bought a pair of AD1865 off Ebay to make a balanced dac for use with IanCanada's I2S to Pcm board.)
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Old 5th September 2018, 04:49 PM   #5
3lite is offline 3lite  Poland
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Quote:
Originally Posted by batteryman View Post
Very impressive. I would not know where to start designing something this sophisticated but I prefer the sound of NOS balanced TDA1541 and AD1865. (just bought a pair of AD1865 off Ebay to make a balanced dac for use with IanCanada's I2S to Pcm board.)
I do not believe you should rule out this digital filter based on your previous experience of generic digital filters This one was created without sacrificing anything like those generic ones do (e.g. size of an accumulator which is way less than required multiply result width, thus resulting in heavy rounding errors). Not to mention the MAC units of 32x35 within this filter.

Having to choose between generic digital filters is like having to choose whether you want your leg or your hand to be cut out (losing digital information due to lack of precision). That is no longer the case
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Old 5th September 2018, 05:43 PM   #6
3lite is offline 3lite  Poland
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This is how I did test PCM56 with a 768 kHz stream:

Click the image to open in full size.

Click the image to open in full size.

Click the image to open in full size.

This is how a reconstructed 20 kHz sine wave looks like with a simple 2rd order Sallen-Key low pass filter:

Click the image to open in full size.

And this how 10 kHz (far from 20 kHz) looks like on NOS zero-order hold DAC (one of the old projects of mine):

Click the image to open in full size.

Obviously DAC in an universal board is not a DAC, but it was for a test purpose Anyway, as you can see the frequency LRCK is operating at is always constant it depends on the provided MCLK signal. This is how latching works - it is always constant and as jitter free as possible (it depends what kind of MCLK signal you do provide).

I did study all possible approaches to DACs. That is including NOS as zero-order hold and "NOS" as first-order hold done in a hardware (the same approach as within the well known thread Building the ultimate NOS DAC using TDA1541A). There is a reason why this custom digital filter was created for and it certainly wasn't done on a whim
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Old 5th September 2018, 06:41 PM   #7
analog_sa is offline analog_sa  Europe
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16x Digital interpolation filter - drive PCM56, PCM58, AD1865 and so on up to 768 kHz
This is just ultracool.
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Old 5th September 2018, 10:27 PM   #8
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by 3lite View Post
I do not believe you should rule out this digital filter based on your previous experience of generic digital filters This one was created without sacrificing anything like those generic ones do (e.g. size of an accumulator which is way less than required multiply result width, thus resulting in heavy rounding errors). Not to mention the MAC units of 32x35 within this filter.

Having to choose between generic digital filters is like having to choose whether you want your leg or your hand to be cut out (losing digital information due to lack of precision). That is no longer the case
Two rather basic features that appear to be missing from almost all digital filter chips on the market are headroom for intersample overshoots and filter responses that actually prevent imaging from the Nyquist frequency onwards, not just imaging above 0.55 fs. What is your take on that?

Besides, did you include an optional apodizing filter for those who believe in apodization?
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Old 5th September 2018, 10:38 PM   #9
3lite is offline 3lite  Poland
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Quote:
Originally Posted by MarcelvdG View Post
Two rather basic features that appear to be missing from almost all digital filter chips on the market are headroom for intersample overshoots and filter responses that actually prevent imaging from the Nyquist frequency onwards, not just imaging above 0.55 fs. What is your take on that?

Besides, did you include an optional apodizing filter for those who believe in apodization?
There is an internal attenuation of the signal by 1 dB. Also, take a look at the first post - I did include white noise test in there. As you can see for 44.1 kHz input does start attenuating at 20 kHz resulting in way over 140 dB of attenuation by 20.5 kHz. Far from Nyquist frequency of 22.05 kHz.

Regarding anodizing - I assume you mean the window function to reduce pre-ringing. The current set of coefficients was created using a Kaiser window. However, I do plan to implement a minimum phase filter as well, but I don't believe it will be switchable, so just a solid set of coefficients programmed into the device according to someone's preferences.
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Old 5th September 2018, 11:50 PM   #10
3lite is offline 3lite  Poland
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Anyway, speaking of minimum phase filter and users who do not like pre-ringing as mentioned. Below is a conversion from a L=16384 taps linear phase filter to minimum phase filter with L=8192:

Click the image to open in full size.

White noise @ 44.1 kHz (a bit cut out, sorry about that):

Click the image to open in full size.

It's pretty much the same as on the chart.

20 kHz:

Click the image to open in full size.

That's a PCM58.

All measurements are pretty much the same as with the linear phase filter. However, certainly it will sound different
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