Integral nonlinearity (INL), THD, etc., in multi-bit DACs

[Alexandre]

they are dismounted using hot-air and this process often degrade parameters or destroy smd chip ...

Thanks, good to know. I had no idea.

(I have a bunch of AD1862N-J, a few TDA1541A, AD1865. But the complexity of the implementation is a turn off for me since I have such a good result with the TDA1543)

 

[scott wurcer]

It takes longer (or never) to remove at lower temps with air, we only use it to remove already dead chips.

A low jitter clock (<1 ps) is a precondition to discover the differences in full proportions.

Dave Greisinger showed that the non-uniformity of sound propagation in an average venue is orders of magnitude worse than this.

 

[PaulFrost]

Simply put, proof is in the pudding, and there's a bunch of modern dac chips that supersede these from Analog Devices, especially for audio applications.

Given the multibit obsession on diyaudio has not been one pushed by the folks with the technical wherewithal, its no surprise that no one has worked with these chips.

I think a major difficulty with multi-bit DACs for the DIY scene is conversion of the I2S to the various DAC digital controls (SPI, I2C, parallel). Generally this requires a DSP or MCU to convert, then you need to deal with jitter and FIFO buffers etc.

 

[dmills]

On the RF DAC thing, one easy way to deal with the poor VLF performance is to simply do the following, seeing as you have an FPGA in play anyway....

After the interpolation up to some suitable RF rate (Maybe 100MHz or so, I will use 100MHz here for the purpose of exposition), one 'multiplies' the sample stream by the sequence {1,0,-1,0} which is clearly a cosine wave of Fs/4 (25Mhz), you could also use {0.707, 0.707, -0.707, -0.707} which is the 45 degree shifted version but that would require real multipliers where the {1,0,-1,0} is pretty trivial.

Thus at the output of the DAC you have not DC-20KHz, but a 40KHz wide double sideband suppressed carrier signal centred at 25MHz plus a mess of low frequency noise.

How does this help?

You know the exact frequency and can in fact trivially drive this frequency out on a couple of FPGA pins, which you connect to a simple H mode mixer based on a couple of jfets or a bus switch and a small RF transformer.

This mixes the 25MHz down to DC, while at the same time mixing all the 1/F and related low frequency noise up to 25MHz.

A simple LC filter following the switching mixer gets you your 1V of audio into 50 ohms which you bridge with the output.

I2S to other things is trivial with a small FPGA (an LX9 is probably ample).

Just a thought.

Regards, Dan.

 

[Alexandre]

I2S to other things is trivial with a small FPGA (an LX9 is probably ample).

Absolutely. I still use a CPLD with only 100 macrocells for that. I can make "balanced inside chip" or "parallel inside chip" operation for the stereo TDA chips or the AD1865, I can also transform the digital stream into a halved bitclock (32fs rather than 64fs, and the 16 bits of data are "stretched" accordingly ).

The lines are reclocked with 74HC logic outside the cpld, with a local crystal oscillator.

As of lately I went back to single ended, not paralleled TDA1543, using only the better channel... sounds excellent. With the worse channel in parallel, I get the +6dB, but also a noise increase (noisy channel) and it doesn´t sound as delicate and resolved. I also did a number of experiments. With a couple of my TDA1543A chips I can parallel and invert one channel and I cancel the sound completely meaning the two channels match exactly. Impossible with the plain TDA1543, because the channels are not simultaneous. We and Richard have discussed this.

(I should add (for Richard) that the continous calibration dacs like TDA1387 seem to sound a bit better at 88.2Khz / 32fs bitclock, even if I am feeding 44.1KHz data, it repeats each sample, get it? I imagine it´s because of more frequent calibration. With the '1543 I use non-oversampling, halved bitclock and it sounds great.)

Another important thing with the TDA1387 is to get the supply voltage just right. Use a variable voltage and adjust it for the lowest clock feedthrough at the analog output. That is the noise of the continous calibration process coming through, because internally the "bits" get disconnected from the analog out and calibrated, one by one, and then connected back - there is a voltage jump and you can minimize it by tweaking either the voltage at the analog out or the +V supply voltage. Adjust for minimum clock noise.

Sorry if this borders on offtopic, I am just looking to share some experiences.

 

[xx3stksm]

RFM

Thank you for your suggestion, dmills. I also thought about some RF modulation to get rid of poor VLF performance. AD9747(16 bit 250MHz) has excellent SNR in RF and an internal switch to make a return to zero signal and mix, which means the output is inverted every half clock cycle. The mix can easily modulate audio signal. But I'm not an expert on RF and don't know whether RF transformer has low enough THD for an audio application or not. That's why my second attempt to try generic pcm1704 was baseband solution.

DAC topology has now shifted from multi-bit to DSM. The third one may be radio frequency modulation DAC like this. It's very interesting to listen RFM DAC in the future. My third approach to design generic pcm1704 must be RFM.

 

[DPH]

I think a major difficulty with multi-bit DACs for the DIY scene is conversion of the I2S to the various DAC digital controls (SPI, I2C, parallel). Generally this requires a DSP or MCU to convert, then you need to deal with jitter and FIFO buffers etc.

Yeah, I didn't mean it so much as a slight as doing a dac right from top to bottom and not using someone's kit requires a good amount of work on a lot of different fronts. Getting a good 4 layer board is tough for many of us too. (I'm not good at layout, basically no practice.)