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General DAC design rules, layout techniques, etc.
General DAC design rules, layout techniques, etc.
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Old 6th December 2017, 07:42 AM   #1
zarandok is offline zarandok  Austria
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Default General DAC design rules, layout techniques, etc.

I have decided to open this topic because of some not fully understood (at least for me) phenomenon in term of DAC designing, (HF) layout rules and so on...

Primarily without specified IC manufacturers, but of course by practical examples we must mention this things for a better understanding.

It can be referred to or quoted from literature (books, manufacturer app. notes), and/or posting some own or foreign designs (please be aware of copyrights) to presenting detail solutions.


Some points for example:

- applying copper pour and determine clearance by HF signals (e.g. I2S lines) to avoid unwanted stray capacitance that degrades signal quality

- proper determining of I2S resistors at the DAC input pins (to prevent overshooting in the signal edges)

- importance of Vref (reference voltage), what type of current they exactly need (datasheets do not give too much informations about that e.g. by AK44xx DACs)

- ground connenction of bypass caps (bigger electorites and small ceramics): simply to common ground pour or preferred a star grounding terminology?

- ...


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Old 6th December 2017, 08:07 AM   #2
abraxalito is online now abraxalito  United Kingdom
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Having done a few DAC layouts myself this looks a little bit ambitious because you're keeping it so generic. My suggestion would be to work from a specific example layout with a particular DAC chip towards general principles. The simpler the DAC chip the better, to begin with.
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Old 6th December 2017, 08:52 AM   #3
zarandok is offline zarandok  Austria
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Ok, let's start...

My actual project (my 2nd DAC) is a multichannel AK4458, for an active speaker. The concept is 2 boards with 10x10cm, one for the DAC and the other for the output filter OPSs, under them.

If I fill the PCB with copper pour, what is the desirable clearance value? The manufacturer can produce down to 6mil I think. My actual setup is 15mil. I ask this because Iíve read the slyp173 document from TI (www.ti.com/lit/ml/slyp173/slyp173.pdf) that writes that we must take care about stray capacitance by HF signals (it can degrade the signal shape). This means for us that at the digital I2S lines, especially at the system clock (>1Mhz) we should avoid the pouring around this lines? On the bottom side I would keep the ground plane anyway because of reducing the current loops (impedance).
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Old 6th December 2017, 09:26 AM   #4
zarandok is offline zarandok  Austria
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I2S resistors at the DAC input:

How can I determine the optimum value? These resistors are for reducing the overshooting of the HF signals rising edge. Should I experiment with different values and check with oscilloscope? Or simply use e.g. 50 Ohms? I have originally placed on the PCB patterns for SMD and through-hole resistors too for easier changing by experimenting with them. But I’m considering to leave them because of the pads on the bottom layer, they make shortage on the ground pour for HF returning currents.

(The boards have only 2 layers. For my 2nd project it will be enough...)

Last edited by zarandok; 6th December 2017 at 09:28 AM.
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Old 6th December 2017, 07:01 PM   #5
rsavas is offline rsavas  Canada
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Your talking about source series termination, usually you chose the R to be the same as the transmission line Z, but in practice you can use a scope to fine tune the R to reduce/damp the ringing.
Another technique is to use some thevenin terminations, they can limit the V swing,slew and thus reduce emissions.
I find changing smt R's a lot easier/faster than a TH R, I use two irons with small tips, and heat both pads at the same time, takes seconds.
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Old 6th December 2017, 07:52 PM   #6
zarandok is offline zarandok  Austria
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Thanks rsavas!
I've decided to delete the through-hole axial resistor pads and keep only the smds.

I'd like to have the option of U.FL coax connector in that case I apply an external clock. (Currently I will drive the DAC with miniDSP USBstreamer, it can operate only in master mode). But if I place this terminal, should I after (like in the picture) or before the termination resistors??
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Old 6th December 2017, 07:57 PM   #7
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by zarandok View Post
Some points for example:

- applying copper pour and determine clearance by HF signals (e.g. I2S lines) to avoid unwanted stray capacitance that degrades signal quality

- proper determining of I2S resistors at the DAC input pins (to prevent overshooting in the signal edges)
I usually start with checking the characteristic impedance of the line and the ground plane below it, using online transmission line calculators or the calculator in KiCAD. I then check how much clearance to copper pour on the same layer is needed to keep it from changing the characteristic impedance significantly. Resistors at outputs can simply get a value equal to the impedance of the line minus the (estimated typical) output impedance of whatever is driving the line. I have no idea about resistors at DAC inputs.

Quote:
Originally Posted by zarandok View Post
- importance of Vref (reference voltage), what type of current they exactly need (datasheets do not give too much informations about that e.g. by AK44xx DACs)
It's extremely important to have a clean reference, because variations of the reference amplitude-modulate your signal, thereby producing undesired sidebands. With noise shaping, high-frequency rubbish on the reference can frequency-convert out-of-band noise into the audio band. I can't help you with poor datasheets, unfortunately.

Quote:
Originally Posted by zarandok View Post
- ground connection of bypass caps (bigger electrolytes and small ceramics): simply to common ground pour or preferred a star grounding terminology?
There are more strategies that work, but if you can keep the loop area small, it is usually a good idea to connect them to the supply (or reference) pin and ground pin you want to decouple and then straight to the ground plane at one point. That is, you make a small local loop that connects to the plane at one point.
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Old 7th December 2017, 07:10 AM   #8
zarandok is offline zarandok  Austria
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Thanks MarcelvdG!
I didn't know KiCAD, but I will see this calculator tool... (I use DipTrace). Thanks for the tip!

I know that reference voltage is extreme important. I'll use low-noise shunt regs near to the DAC chip to supply them, possibly will try LT3042 too sometime...

The reason why I asked this question is that I have the small bypass caps on the bottom layer, and then connected the Vref line through vias to the DAC pins (see picture). This is of course not the best solution, because of vias have some inductance which could decreace the effect of the bypass caps -> IF the Vref pins need HF currents! And this is the point what I do not know, where the HF currents are flowing into the DAC. At the Vref pins or at the AVDD pin (by AK4458 for example)??
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Old 7th December 2017, 11:11 AM   #9
zarandok is offline zarandok  Austria
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Ok, calculated without guarding on the top side. And what now...?
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Old 7th December 2017, 12:39 PM   #10
synonymous is offline synonymous  United States
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wackdac.png

I find it best as compact as possible.
less than 3cm square
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