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ES9038Q2M Board
ES9038Q2M Board
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Old 27th November 2020, 09:56 PM   #6231
Markw4 is offline Markw4  United States
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Maybe it only applies to sync mode if entered by way of enabling 128_fs mode? (In that case there is the presumption of an external PCM interpolation filter.)

I believe sync mode can be entered by other means, which includes setting DPLL Bandwidth=0. In that case, if lock fails then a mute condition will occur.

Last edited by Markw4; 27th November 2020 at 10:03 PM.
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Old 27th November 2020, 10:01 PM   #6232
potstip is offline potstip  Turkey
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Hello Mark;

Thanks actually i am not using USB so it not possible for me to switch between clocks. So i have to stick with ASRC. I will use NZ2520SDA series clock. So regarding to clock selection i guess with 24.576Mhz i can not able to get 192Khz. Because acc to your comment here below on post #2058
"To figure out the maximum PCM/I2S sample rate you could get with a particular clock, divide the clock frequency by 192."

I can only reach 128Khz with 24.576Mhz clock. So i guess i have to go with 49,152Mhz.
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Old 27th November 2020, 10:08 PM   #6233
Markw4 is offline Markw4  United States
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Potstip,
It depends on the clock frequency specifications which are near the end of the datasheet. For async, IIRC MCLK has to be greater than 3 times the bit clock frequency. Been awhile since I looked at it though. For sync mode, again IIRC, MCLK is equal to 2 times BCLK or an integer multiple of that. Study the data sheet and you should be able to figure out what to try. If necessary I could review it again but I'm not here to do all the work for you.

EDIT: The native mode of the dac is 32-bit, which is probably something to keep in mind.

Last edited by Markw4; 27th November 2020 at 10:26 PM.
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Old 28th November 2020, 03:48 PM   #6234
altor is offline altor  Israel
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Quote:
Originally Posted by Markw4 View Post
I believe sync mode can be entered by other means, which includes setting DPLL Bandwidth=0. In that case, if lock fails then a mute condition will occur.
Not necessary to set DPLL=0 (DPLL_PCM and DPLL_DSD) because one bit in the next register can disable it at all.

P.S. Despite that DS says "no" DSD works in Sync Mode, at least <=dsd256.
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Old 28th November 2020, 04:01 PM   #6235
Markw4 is offline Markw4  United States
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Seems to me Allo claims they have ES9038Q2M master sync mode working with DSD and DPLL Bandwidth=0. They had to work with ESS and XMOS to solve one problem that turned out to be an XMOS coding error affecting master sync mode with DSD, at least IIRC.
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Old 28th November 2020, 04:17 PM   #6236
altor is offline altor  Israel
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Did not use 9038Q2M, I made it with 9038Pro.
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Old 28th November 2020, 04:37 PM   #6237
meszarosa is offline meszarosa  Hungary
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ES9038Q2M Board
Quote:
Originally Posted by altor View Post
Not necessary to set DPLL=0 (DPLL_PCM and DPLL_DSD) because one bit in the next register can disable it at all.



P.S. Despite that DS says "no" DSD works in Sync Mode, at least <=dsd256.
I've tried DSD256(FS=11.2MHz) on ES9038Q2M(in slave mode), feeding es9038 with 2xFS, no success in async mode, but also no success in sync mode (DPLL=0). No sound. Any hints, how to make it work?
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Old 28th November 2020, 04:55 PM   #6238
Markw4 is offline Markw4  United States
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In async mode MCLK clock needs to be faster than for sync mode. There is a table near the end of the data sheet with info on that. Otherwise, for DSD256 in async mode you might try a 45MHz MCLK.
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Old 28th November 2020, 05:17 PM   #6239
meszarosa is offline meszarosa  Hungary
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Quote:
Originally Posted by Markw4 View Post
In async mode MCLK clock needs to be faster than for sync mode. There is a table near the end of the data sheet with info on that. Otherwise, for DSD256 in async mode you might try a 45MHz MCLK.
I've tried : async mode with 45MHz works fine. (DPLL=1 stable) However, I've tried to divide down this 45MHz clock with a DFF to feed the DSD source (Ak4137), so the DAC and the DSD source were quasi-sync, but I had no success putting the ES9038Q2M in DPLL=0 mode (sync).
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Old 28th November 2020, 06:55 PM   #6240
Markw4 is offline Markw4  United States
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AK4137 actually uses a PLL to resample, despite allowing a reference clock which can help with stability. Therefore, some jitter can be present on the output. You might try reclocking the signals before they go into the dac. You might also try cleaning up power to AK4137 and any chips that pass digital audio to/from it.
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