If you only want 192kHz PCM, and if using a 24MHz clock, then synchronous might be an option. If you want 44.1kHz family sample rate support and if using a 24MHz clock, then ASRC would be needed for that.
So long as the clock frequency is high enough to support the incoming audio sample rate, ASRC will convert all incoming digital audio to use the dac chip clock for playback. By default it does that automatically.
So long as the clock frequency is high enough to support the incoming audio sample rate, ASRC will convert all incoming digital audio to use the dac chip clock for playback. By default it does that automatically.
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Actually i need both 44.1 and 48 khz family and maximum 192Khz.
But evo board also use single 50Mhz osc. So single clock suppose to be support both families i guess.
Single clock can support both families only in Async. mode (with ASRC).
If you use I2S input and ant to use bot families in Sync. mode, you must use 2 oscillators (22.528 and 24.576 for PCM192), and be able to switch them, according to the PCM sample rate.
P.S. Does anybody try to use Sync.Mode for DSD? Datasheet says "no", but maybe? (not really understand why not)
potstip,
With a 24MHz clock you could run 48kHz family sample rates in sync mode and 44kHz family in async mode. The USB board can tell you which it is using the F0 - F3 signals. Your MCU just needs to be able to make the switch fast enough. Of course, you would hear likely hear the difference in sound quality if the dac board was well enough designed. In that case you might not be satisfied with the sound of 44kHz family sample rates.
With a 24MHz clock you could run 48kHz family sample rates in sync mode and 44kHz family in async mode. The USB board can tell you which it is using the F0 - F3 signals. Your MCU just needs to be able to make the switch fast enough. Of course, you would hear likely hear the difference in sound quality if the dac board was well enough designed. In that case you might not be satisfied with the sound of 44kHz family sample rates.
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Maybe it only applies to sync mode if entered by way of enabling 128_fs mode? (In that case there is the presumption of an external PCM interpolation filter.)
I believe sync mode can be entered by other means, which includes setting DPLL Bandwidth=0. In that case, if lock fails then a mute condition will occur.
I believe sync mode can be entered by other means, which includes setting DPLL Bandwidth=0. In that case, if lock fails then a mute condition will occur.
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Hello Mark;
Thanks actually i am not using USB so it not possible for me to switch between clocks. So i have to stick with ASRC. I will use NZ2520SDA series clock. So regarding to clock selection i guess with 24.576Mhz i can not able to get 192Khz. Because acc to your comment here below on post #2058
"To figure out the maximum PCM/I2S sample rate you could get with a particular clock, divide the clock frequency by 192."
I can only reach 128Khz with 24.576Mhz clock. So i guess i have to go with 49,152Mhz.
Thanks actually i am not using USB so it not possible for me to switch between clocks. So i have to stick with ASRC. I will use NZ2520SDA series clock. So regarding to clock selection i guess with 24.576Mhz i can not able to get 192Khz. Because acc to your comment here below on post #2058
"To figure out the maximum PCM/I2S sample rate you could get with a particular clock, divide the clock frequency by 192."
I can only reach 128Khz with 24.576Mhz clock. So i guess i have to go with 49,152Mhz.
Potstip,
It depends on the clock frequency specifications which are near the end of the datasheet. For async, IIRC MCLK has to be greater than 3 times the bit clock frequency. Been awhile since I looked at it though. For sync mode, again IIRC, MCLK is equal to 2 times BCLK or an integer multiple of that. Study the data sheet and you should be able to figure out what to try. If necessary I could review it again but I'm not here to do all the work for you.
EDIT: The native mode of the dac is 32-bit, which is probably something to keep in mind.
It depends on the clock frequency specifications which are near the end of the datasheet. For async, IIRC MCLK has to be greater than 3 times the bit clock frequency. Been awhile since I looked at it though. For sync mode, again IIRC, MCLK is equal to 2 times BCLK or an integer multiple of that. Study the data sheet and you should be able to figure out what to try. If necessary I could review it again but I'm not here to do all the work for you.
EDIT: The native mode of the dac is 32-bit, which is probably something to keep in mind.
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Not necessary to set DPLL=0 (DPLL_PCM and DPLL_DSD) because one bit in the next register can disable it at all.
P.S. Despite that DS says "no" DSD works in Sync Mode, at least <=dsd256.
I've tried DSD256(FS=11.2MHz) on ES9038Q2M(in slave mode), feeding es9038 with 2xFS, no success in async mode, but also no success in sync mode (DPLL=0). No sound. Any hints, how to make it work?
I've tried : async mode with 45MHz works fine. (DPLL=1 stable) However, I've tried to divide down this 45MHz clock with a DFF to feed the DSD source (Ak4137), so the DAC and the DSD source were quasi-sync, but I had no success putting the ES9038Q2M in DPLL=0 mode (sync).
AK4137 actually uses a PLL to resample, despite allowing a reference clock which can help with stability. Therefore, some jitter can be present on the output. You might try reclocking the signals before they go into the dac. You might also try cleaning up power to AK4137 and any chips that pass digital audio to/from it.