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Is DSD signed or unsigned?
Is DSD signed or unsigned?
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Old 17th September 2017, 08:54 AM   #1
MarcelvdG is offline MarcelvdG  Netherlands
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Default Is DSD signed or unsigned?

Does anyone know whether the single bit stream of a DSD signal is to be interpreted as:

A. Just a series of simple unsigned bits, so 1 > 0

or

B. A stream of sign bits of very short two's complement words, so 1 means negative and 0 means not negative?

I've always assumed A, but that's not based on anything, and a colleague of mine tends to see sigma-delta modulates as rows of single-bit signed numbers.

My apologies for posting this twice; I had accidentally put it in the wrong forum and didn't manage to delete it anymore.
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Old 18th September 2017, 06:20 AM   #2
xx3stksm is offline xx3stksm  Japan
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Hi, I also need to apology. I carelessly posted to the wrong forum. I think a moderator can fix the problem.
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Old 18th September 2017, 07:12 PM   #3
MarcelvdG is offline MarcelvdG  Netherlands
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Thanks for the answer (on the other forum). It seems that analogue designers usually think that 1 > 0, while digital designers regard the single bit as a sign bit. I wonder what Sony and Philips wrote in the DSD standard.
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Old 19th September 2017, 07:06 AM   #4
xx3stksm is offline xx3stksm  Japan
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I think DSD is a hybrid between analog and digital. You can regard DSD as an analog signal and convert it to the original signal by simple RC filter. If you regard
DSD as digital one, you design decimation filter to remove HF. Both are theoretically possible to reproduce the original one.

But in a practical solution, I prefer a digital one. I once struggled with a simple solution which converts DSD to analog without a commercial DACs like pcm1792. It means a DAC without DAC chips. I finally gave up. Achieving the performance like pcm1792 is tough by a 1bit converter.

I'm not sure the reason why. The fatal issue probably comes from rise and fall time of analog output. SIM of DSD in digital domain has no rise and fall time. It's excellent performance indeed. But you can't get good SNR in a real circuit. Rise and fall time is something like a glitch which degrades SNR. The amplitude of this glitch is an inverse proportion to bit resolution. DSD is the worst because it always swings from the min to the max or the opposite direction.

I'm not sure low SNR comes from 1 bit. But 2bit is better than 1bit. 5bit or more resolution can outperform pcm1792 even in 1bit operation. If your DSM DAC is 5bits resolution, it forces to work in 1bit when the input is below about 50dB. But the voltage swing is smaller than DSD by 1/32 because their LSB is 1/32. In this case, no degradation of SNR occurs. That's why I think DSD has the fatal problem to be implemented into a simple RC converter.
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Old 19th September 2017, 08:08 PM   #5
MarcelvdG is offline MarcelvdG  Netherlands
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The rise and fall time issue should be solved when you make a return-to-zero DAC. Did you try that? The simplest return-to-zero DAC is a D flip-flop with a NOR gate after it that suppresses the output while the clock is high. You can improve it further by making a FIRDAC, combining a digital delay line and a few elementary DACs of which the outputs are added.

Even then you won't get close to the SNR values of the best commercial DAC chips. You would need a switched capacitor DAC and/or a really long FIRDAC and/or an extremely good clock for that.

As an example of a simple return-to-zero FIRDAC, the attachment is a circuit I'm building. It is a four-tap uniformly weighted FIRDAC with an active low-pass filter behind it. It isn't meant for DSD but for the sigma-delta from the "Clarification of Sigma Delta DAC operation wanted" thread, but with other filter component values it could also be used for DSD. I make it balanced to cancel out the effect of unequal high and low output resistances of the logic gates. The supply for the logic gates comes from a LTC3042 low-noise voltage regulator with a ferrite bead-capacitor filter behind it.
Attached Files
File Type: pdf DACcore-DACcoreL.pdf (93.5 KB, 45 views)
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Old 20th September 2017, 04:28 AM   #6
MarcelvdG is offline MarcelvdG  Netherlands
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I meant LT3042 rather than LTC3042.
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Old 20th September 2017, 07:14 AM   #7
xx3stksm is offline xx3stksm  Japan
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Thank you for your suggestion. Many people around me are a consumer, those who are interested in DIY hardware is rare. I can't get interesting information about DIY even on the internet in Japanese. As long as I know, return to zero is one solution to decrease glitches of a multi-bit DAC because RTZ can cancel different delay of each segment. I can't exactly understand that RTZ has the same effect about 1bit DSM.

What I want to mean in rise and fall time is the difference between ideal pulse and a real one like fig 1. A real pulse has finite rise and fall time. They act as something like a glitch which causes degradation of SNR. Shorter rise/fall time is needed for high SNR more than 100dB. As long as I tested, 1bit converter can't achieve this goal. fig2,fig3,fig4, and fig5 are several attempts I have ever done.

My conclusion is that this type of glitch is the inverse proportion to bit resolution. That's why 1bit can't be superior to a multi-bit. 1bit always has 100% voltage swing. This is the worst situation for "glitch." If you use 5bit, the amplitude of "glitch" becomes 1/32. Those data is measured with the attached pic. I'm going to design a new prototype PCB for this DSM. I can test both 1bit and multi-bit DSM with the new PCB. I'm sure 1bit is almost same as my terrible breadboard.
Attached Images
File Type: jpg fig1.jpg (113.8 KB, 209 views)
File Type: jpg tek00246.jpg (167.5 KB, 211 views)
File Type: jpg tek00247.jpg (169.9 KB, 204 views)
File Type: jpg tek00209.jpg (305.6 KB, 200 views)
File Type: jpg tek00212.jpg (98.2 KB, 198 views)
File Type: jpg IMG_5129.JPG (266.5 KB, 69 views)
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Old 20th September 2017, 10:30 AM   #8
HpW is offline HpW
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Quote:
Originally Posted by MarcelvdG View Post
Does anyone know whether the single bit stream of a DSD signal is to be interpreted as......
1. The bits are given as "1" or "0".

2. This means as level as +1 or -1.

3. To have an idle level, a certain bit sequence is used.

4. To go positive on level: more "1" bit's are used in compare to go negative on level: more "0" bits are used.

Currently on building my DSD generator & analyzer

Hp
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Download FFT Analyzer & Generator at www.hpw-works.com
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Old 20th September 2017, 06:23 PM   #9
MarcelvdG is offline MarcelvdG  Netherlands
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That's great, if Sony and Philips defined that 1 means +1 and 0 means -1, I won't need to update my FPGA code. By mere luck I interpreted it that same way.
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Old 20th September 2017, 06:58 PM   #10
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by xx3stksm View Post
Thank you for your suggestion. Many people around me are a consumer, those who are interested in DIY hardware is rare. I can't get interesting information about DIY even on the internet in Japanese. As long as I know, return to zero is one solution to decrease glitches of a multi-bit DAC because RTZ can cancel different delay of each segment. I can't exactly understand that RTZ has the same effect about 1bit DSM.

What I want to mean in rise and fall time is the difference between ideal pulse and a real one like fig 1. A real pulse has finite rise and fall time. They act as something like a glitch which causes degradation of SNR. Shorter rise/fall time is needed for high SNR more than 100dB. As long as I tested, 1bit converter can't achieve this goal. fig2,fig3,fig4, and fig5 are several attempts I have ever done.

My conclusion is that this type of glitch is the inverse proportion to bit resolution. That's why 1bit can't be superior to a multi-bit. 1bit always has 100% voltage swing. This is the worst situation for "glitch." If you use 5bit, the amplitude of "glitch" becomes 1/32. Those data is measured with the attached pic. I'm going to design a new prototype PCB for this DSM. I can test both 1bit and multi-bit DSM with the new PCB. I'm sure 1bit is almost same as my terrible breadboard.
100 dB is quite ambitious, but I look at the glitch problem in a different way,

What matters in the end is the low-pass filtered signal. Low pass filtering means taking a weighted average, where the weight is defined by the impulse response of the filter. Looking over a time span that is much shorter than the reciprocal of the cut-off frequency, the weight is nearly constant.

The problem is that with unequal tPLH and tPHL, the average of a 1010 sequence differs from the average value of a 1100 sequence, as you can see in the attached figure. That is, your bit weights depend on the surrounding bits. By always returning to zero you circumvent this.

The disadvantage is that you get more transitions, which makes you more sensitive to slight displacements of these transitions, caused by things like clock jitter. A FIRDAC can solve that again.

Multibit is indeed also an option. If your sigma-delta indeed only uses two levels during silence, mismatch will only show up in the distortion figures and not in the ratio between maximum signal and idle channel noise.
Attached Images
File Type: png Figure2.png (1.0 KB, 61 views)

Last edited by MarcelvdG; 20th September 2017 at 07:01 PM.
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