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Valve DAC from Linear Audio volume 13
Valve DAC from Linear Audio volume 13
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Old 23rd September 2020, 12:18 PM   #931
NickKUK is offline NickKUK
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Join Date: Dec 2019
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Originally Posted by NickKUK View Post
Very dumb open question but why not clock the tubes at a high rate (ie 3MHz) then run the digital switching data stream at 192Khz then upscale using software?

Surely this shifts the aliasing and switching/clock harmonics into an easy filterable region?

My limited understanding of valves is that they can happily 'switch' at this speed although circuit design is made more complex due to the increasing RF antenna properties of the tracks. Or is it the voltage required to drive the swings of signal at that rate?
I think I've answered my own question here.

Miles wrote this: Tube rise time and slew rate

And following grid drivers: Design Considerations

Rule of thumb 1:10 with 3MHz -> 333ns/Vsignal swing is better serviced by a 33ns swing. So you'd need to drive the gate to ensure an accurate signal.

In short - doable but exponentially additional cost (adding a power amp grid driver to drive each of the DAC signal tubes).

Still... you know you want to
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Old 23rd September 2020, 12:54 PM   #932
NickKUK is offline NickKUK
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Originally Posted by NickKUK View Post
Still... you know you want to
Last post on this - it looks as if Marcel does this on the crystal oscillator at 27MHz already (using a gate driver).
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Old 23rd September 2020, 06:59 PM   #933
Mikky1975 is offline Mikky1975  Italy
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Originally Posted by agent.5 View Post
Schematics and renders of the external oscillators inputs board and stand-alone, always-on Crystek clock module (2 layers board). Connect 1 or 2 single-ended clocks to J3 and J4 of the inputs board. Using external clocks has been my original plan, and I reused the schematic a couple pages back, and removed the sine-to-square wave converters.
I took a look at your project and, having (partly) understood what you're trying to do, you now have my attention

I'm considering andrea_mori work for the the external clock part: can you confirm you're expecting a cmos square wave as external clock?

Thanks,
Mirko
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Old 23rd September 2020, 07:11 PM   #934
MarcelvdG is offline MarcelvdG  Netherlands
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Join Date: Mar 2003
Location: Haarlem, the Netherlands
Hi Nick,

In the original valve DAC, the bottom differential pair in each DAC core is switching at 27 MHz. The 27 MHz comes from a valve crystal oscillator (ECC81) via two valve buffers (2 times EF80). The digital input signal is converted into a 27 Mbit/s noise-shaped single-bit digital signal that drives the upper differential pairs. This conversion is done by an SRC4392 asynchronous sample rate converter chip and an FPGA board, the grids of the upper differential pairs are driven by a 74AHCT74.

In the raw-DSD version, the bottom differential pair is driven by some solid-state circuitry with either 22.5792 MHz or 24.576 MHz, or a frequency that is 2, 4 or 8 times lower. The upper differential pairs are driven by a 22.5792 Mbit/s or 24.576 Mbit/s or 2, 4 or 8 times lower noise-shaped single-bit digital signal. That signal comes from outside the DAC, Ray generates it with a computer. Level shifting and upper differential pair grid driving is done in the same way as in the original valve DAC.

Filtering aliases and clock harmonics is easy as they are at quite high frequencies, but there is also out-of-band quantization noise due to the conversion to a noise-shaped single-bit signal. That's why the filter cut-off frequency should not be made too high.

As I don't understand your question, I'm not sure if this answers it, but I hope it does anyway.

Regards,
Marcel

Last edited by MarcelvdG; 23rd September 2020 at 07:25 PM.
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Old 23rd September 2020, 07:17 PM   #935
agent.5 is offline agent.5  United States
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Join Date: Aug 2003
Location: San Francisco, CA
Quote:
Originally Posted by Mikky1975 View Post
I took a look at your project and, having (partly) understood what you're trying to do, you now have my attention

I'm considering andrea_mori work for the the external clock part: can you confirm you're expecting a cmos square wave as external clock?

Thanks,
Mirko
yes. Valve Dac needs a TTL/CMOS signal clock. I also am considering a pair of Andrea's well tempered clocks. According to him, these clocks generate sine wave outputs. Sine-to-square wave converters are required.

Last edited by agent.5; 23rd September 2020 at 07:25 PM.
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Old 23rd September 2020, 09:15 PM   #936
NickKUK is offline NickKUK
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Join Date: Dec 2019
Quote:
Originally Posted by MarcelvdG View Post
Hi Nick,

In the original valve DAC, the bottom differential pair in each DAC core is switching at 27 MHz. The 27 MHz comes from a valve crystal oscillator (ECC81) via two valve buffers (2 times EF80). The digital input signal is converted into a 27 Mbit/s noise-shaped single-bit digital signal that drives the upper differential pairs. This conversion is done by an SRC4392 asynchronous sample rate converter chip and an FPGA board, the grids of the upper differential pairs are driven by a 74AHCT74.

In the raw-DSD version, the bottom differential pair is driven by some solid-state circuitry with either 22.5792 MHz or 24.576 MHz, or a frequency that is 2, 4 or 8 times lower. The upper differential pairs are driven by a 22.5792 Mbit/s or 24.576 Mbit/s or 2, 4 or 8 times lower noise-shaped single-bit digital signal. That signal comes from outside the DAC, Ray generates it with a computer. Level shifting and upper differential pair grid driving is done in the same way as in the original valve DAC.

Filtering aliases and clock harmonics is easy as they are at quite high frequencies, but there is also out-of-band quantization noise due to the conversion to a noise-shaped single-bit signal. That's why the filter cut-off frequency should not be made too high.

As I don't understand your question, I'm not sure if this answers it, but I hope it does anyway.

Regards,
Marcel
Yup - it also gives direction for my curiosity
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Old 24th September 2020, 11:10 PM   #937
MarcelvdG is offline MarcelvdG  Netherlands
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Join Date: Mar 2003
Location: Haarlem, the Netherlands
How the signal is digitally converted into a noise-shaped single-bit signal in the original valve DAC is described in more detail in sections 2, 3, 7, 8 and 9 of https://linearaudio.net/sites/linear...V13%20mvdg.pdf

How it is done in the software Ray uses is a trade secret, but from what I've read about it, I get the impression that it is done in a rather similar way although the details will be different. For example, Ray doesn't need any asynchronous sample rate converter because everything is synchronized to the clock that drives his DAC.
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