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Valve DAC from Linear Audio volume 13
Valve DAC from Linear Audio volume 13
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Old 19th January 2021, 05:36 AM   #1341
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by rfbrw View Post
So long as there isn't a Guardian DAC.
Are you afraid they might team up and take control of all the audio equipment in the world?
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Old 19th January 2021, 05:47 AM   #1342
MarcelvdG is offline MarcelvdG  Netherlands
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Originally Posted by nautibuoy View Post
Yes, I was being rather tongue in cheek Marcel. Anyway, my listening room wouldn't be big enough...
I know you were kidding, but still I wanted to explain why I thought of making a softcore Pilot ACE emulator rather than a Colossus emulator. The Pilot ACE is Turing-complete and based on Turing's design.

As far as I remember, the real Pilot ACE is not nearly as big as Colossus, by the way. I saw the rebuilt Colossus in The National Museum of Computing on Thursday 11 June 2015 and the Pilot ACE in the Science Museum in London one day earlier (or later, but I think earlier).
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Old 19th January 2021, 05:49 AM   #1343
acg is offline acg  Australia
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All the bits for my build are either here or ordered, apart from a case, which I will build from scratch once I get an idea of exactly what needs to fit within. Transformers seem like they will be the hold-up, both power and output. Freight comes in as a large part of the overall cost when you live on the opposite side of the world to where the bits need to come from in dribs and drabs.

Am looking forward to the build.
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Old 19th January 2021, 06:00 AM   #1344
nautibuoy is offline nautibuoy  United Kingdom
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A visit to Bletchley is still on my 'bucket list' - it should have been last summer but...

Such a shame that so much of the original Bletchley kit was apparently destroyed in 1945/46 - imagine thinking that you could put the genie back in the bottle.

Anyway, if things improve maybe this summer, coupled to a visit to the Shuttleworth Collection (pretty sure I mentioned that to you before);

Shuttleworth Collection | Shuttleworth
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Old 19th January 2021, 06:22 AM   #1345
MarcelvdG is offline MarcelvdG  Netherlands
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Even the huts on Bletchley Park were nearly demolished and the entire sire redevelopped. Thank goodness that didn't happen!
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Old 19th January 2021, 06:32 AM   #1346
rfbrw is offline rfbrw
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Originally Posted by MarcelvdG View Post
Are you afraid they might team up and take control of all the audio equipment in the world?
We should be so lucky that they would stop there.
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Old 19th January 2021, 06:03 PM   #1347
MarcelvdG is offline MarcelvdG  Netherlands
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This is my proposal for a 4:1 I2S multiplexer, version with only 3.3 V CMOS inputs. It can be changed into LVDS for BCK, LRCK and data (SD) by replacing the A sections of the 74LVC244As with a quadruple LVDS receiver with three-state CMOS outputs, such as the SN65LVDT390ADBT. The 74LVC74A's are meant to ensure safe clock switching for the bit clock. The 74HC14 debounces the signals from the switch. C8 and C9 are meant to prevent hold time issues. Use at your own risk, as the circuit has not been tried, tested or simulated.
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Last edited by MarcelvdG; 19th January 2021 at 06:25 PM.
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Old 19th January 2021, 06:40 PM   #1348
Markw4 is offline Markw4  United States
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Regarding I2S multiplexers, IME they can add jitter to I2S signals. Careful power supply design and decoupling can help quite a bit. Nothing probably helps as a much as a reclock after the mux. Perhaps the dac already does that?
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Old 19th January 2021, 07:11 PM   #1349
MarcelvdG is offline MarcelvdG  Netherlands
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I forgot to mention explicitly that the circuit of post #1347 is meant for the original valve DAC, where the signal first goes into an FPGA module, then into an asynchronous sample rate converter, then back into the FPGA module, then gets reclocked twice by flip-flops and then gets retimed by a current-steering valve logic gate.

For the raw DSD valve DAC, I would recommend a clearer separation between the data handling and the clock handling part. Unfortunately that would probably lead to a larger skew, as the data and bit clock or master clock can't be buffered by the same ICs when you want to keep them well-separated. It may then be necessary to add extra delay circuits and/or reclocking flip-flops to solve hold time issues.
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Old 20th January 2021, 03:11 AM   #1350
acg is offline acg  Australia
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FPGA has arrived Marcel. Many thanks.
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