Valve DAC from Linear Audio volume 13

[acg]

Your proposed solution is much neater Marcel. And much more desirable.

[Tix88]

Hi Marcel, have you ever thought, if available, to implement LEDs or a display for reading the input signals and formats?

[Raj1]

Originally Posted by Tix88

Hi Marcel, have you ever thought, if available, to implement LEDs or a display for reading the input signals and formats?

You can find usb to i2s modules that offer support for such features.

[MarcelvdG]

Originally Posted by Tix88

Hi Marcel, have you ever thought, if available, to implement LEDs or a display for reading the input signals and formats?

When I thought about the user interface, I had a temporary obsession with the life and work of Alan Turing. I considered implementing a Pilot ACE emulator as a softcore microcontroller with the remaining FPGA resources and using that to make a nice user interface with an alphanumeric display and everything (no punched card reader, though).

I soon realized that doing so would mean at least another year of spending most of my spare time writing and debugging Verilog code and writing Pilot ACE machine language. I decided that I did not really want that and that it was time to snap out of Aspie++ mode. Hence the decision to just make a very basic interface with a few knobs and lamps.

You could decide to do what I didn't, though. As long as you come up with a user interface that needs no more than the 23 FPGA I/Os that I use for my knobs and lamps, you can just remove the neon lamp and switch interface circuits (ZTX558-circuits for the neon lamps and 330 ohm-1 nF low-pass filters for the switches) and connect the I/Os to whatever you want to connect them to. You can then modify the Verilog code and use the remaining FPGA resources to implement your user interface, either directly with state machines or via a softcore microcontroller. My Verilog code is available on Downloads | Linear Audio and everyone is very welcome to modify it as they like.

[nautibuoy]

Gosh Marcel, next you'll be designing a Colossus DAC.

[MarcelvdG]

By the way, for debugging purposes, I sent signals to user LEDs on the FPGA module that indicate that the sampling rate is greater than 90 kHz, 100 kHz and 190 kHz. To be precise, there is a little hysteresis and the actual thresholds are:

90 kHz and 90.98567818 kHz
98.991750687 kHz and 100 kHz
189.973614776 kHz and 190.98143236 kHz

It would be quite straightforward to send those signals to three of the neon lamps. If you don't want to use the surprise mode, it only requires a change in the user constraints file and going through the steps of the FPGA synthesis process. If you do want to use the surprise mode, it is a very minor change to the Verilog code and going through all the steps of the FPGA synthesis process.