Hi, I posted a few months ago about a FPGA-based digital-to-analog converter, and I'm happy to say that I've made a lot of progress.
I have two working versions, one uses a board by the company Digilent called the "CMOD A7" that's a breadboard-able Xilinx FPGA. It only has USB connectivity via a serial connection so I set it up to play PCM data sent over that line, and made a little Python driver script. It's flow controlled, so there's no bit slip due to the interface--everything's re-clocked on the FPGA and buffered there. On Linux you can even tell ALSA to redirect all sound to the script so it's more like a sound card.
The other version uses a similar board by Trenz Electronics that includes an ARM core alongside the FPGA (Xilinx's Zynq technology) and plays WAV files off a microSD card, mp3-player style (support for compressed formats is proving difficult due to limited available memory... if anyone knows of decoders that will work with less than 256K holler!)
Both of the boards suffer from electrical noise that dominates the DACs response, so my next step is to design a custom board more suited to analog signals--but these are nice proofs of concept that it's possible.
It's all dependent on the Xilinx tools, but those are free (although I believe there are export restrictions, ymmv.) The modulator, UART, and software I wrote myself -- optionally, it's easy to plug in a CIC or FIR interpolation block between the buffer and the output and Xilinx provides canned solutions for both. I'm not an expert in the topic, but I haven't gotten satisfactory gains from including either. It's something I want to look into.
The DAC logic itself is quite simple, set up as a Delta-Sigma modulator with one, two, or three delta registers and flexible coefficients. Something I've learned from this is that there's definitely multiple ways to skin the hog, extensive simulation and testing still has me waffling between the way different modulation schemes sound. (Right now I'm listening to what I've termed [+1,+1] and it has beautiful low-end response but, sadly, audible distortion in extremely quiet passages.)
The flexibility and ease of A-B testing is, in my humble opinion, the best feature of this whole thing--I can listen and test different architectures back-to-back with ease.
This is getting long, but I wanted to end by saying if folks are interested, I'm more than willing to hook anyone up with source code and "getting started" info.
-Noah
I have two working versions, one uses a board by the company Digilent called the "CMOD A7" that's a breadboard-able Xilinx FPGA. It only has USB connectivity via a serial connection so I set it up to play PCM data sent over that line, and made a little Python driver script. It's flow controlled, so there's no bit slip due to the interface--everything's re-clocked on the FPGA and buffered there. On Linux you can even tell ALSA to redirect all sound to the script so it's more like a sound card.
The other version uses a similar board by Trenz Electronics that includes an ARM core alongside the FPGA (Xilinx's Zynq technology) and plays WAV files off a microSD card, mp3-player style (support for compressed formats is proving difficult due to limited available memory... if anyone knows of decoders that will work with less than 256K holler!)
Both of the boards suffer from electrical noise that dominates the DACs response, so my next step is to design a custom board more suited to analog signals--but these are nice proofs of concept that it's possible.
It's all dependent on the Xilinx tools, but those are free (although I believe there are export restrictions, ymmv.) The modulator, UART, and software I wrote myself -- optionally, it's easy to plug in a CIC or FIR interpolation block between the buffer and the output and Xilinx provides canned solutions for both. I'm not an expert in the topic, but I haven't gotten satisfactory gains from including either. It's something I want to look into.
The DAC logic itself is quite simple, set up as a Delta-Sigma modulator with one, two, or three delta registers and flexible coefficients. Something I've learned from this is that there's definitely multiple ways to skin the hog, extensive simulation and testing still has me waffling between the way different modulation schemes sound. (Right now I'm listening to what I've termed [+1,+1] and it has beautiful low-end response but, sadly, audible distortion in extremely quiet passages.)
The flexibility and ease of A-B testing is, in my humble opinion, the best feature of this whole thing--I can listen and test different architectures back-to-back with ease.
This is getting long, but I wanted to end by saying if folks are interested, I'm more than willing to hook anyone up with source code and "getting started" info.
-Noah
Maybe upsample and add some dither beforehand. Adobe Audition maybe? See if that makes any difference.
You could also power Cmod A7 up with an external 3.3 -5.5V, so I suggest giving that a try, in an attempt to obtain better noise performance.... shunt regulator would work really nice here.
A FPGA GPIO, yeah. It's shocking that it works, honestly. But it does.
I want to try a reclocking flip-flop on a clean supply, but I haven't yet.
Right now I'm focused on digital filtering possibilities.
Edit: the very low tech solution of a powered USB hub helped a lot with background noise.
I want to try a reclocking flip-flop on a clean supply, but I haven't yet.
Right now I'm focused on digital filtering possibilities.
Edit: the very low tech solution of a powered USB hub helped a lot with background noise.
Hi Noah, did you read this?
https://www.ee.usyd.edu.au/people/philip.leong/UserFiles/File/papers/dac_fpt03.pdf
The paper is called "An FPGA-based Re-configurable 24-bit 96kHz Sigma-Delta Audio DAC", but it's already pretty old (2003) and not too much details.
It describes their Sigma-Delta DAC with a 64x/128x/192x interpolator, 3th or 5th order SDM.
They tested it on two boards: One is a "Celoxica RC200" with a Xilinx Virtex II XC2V1000. The other their own "Pilchard" memory interface board with a Xilinx XCV1000E. That board seems to be designed for data processing (mainly cryptograhy, it seems).
But they claim a extreme good SNR (up to 170db at low playing levels; but 115db seem more likely for realistic scenarios).
Due to the rather dodgy quality of the paper, and since I could not find a follow-up paper (seems they did that for a conference), I suppose that was the work of a student who decided he could build a DAC for home use and his final thesis
https://www.ee.usyd.edu.au/people/philip.leong/UserFiles/File/papers/dac_fpt03.pdf
The paper is called "An FPGA-based Re-configurable 24-bit 96kHz Sigma-Delta Audio DAC", but it's already pretty old (2003) and not too much details.
It describes their Sigma-Delta DAC with a 64x/128x/192x interpolator, 3th or 5th order SDM.
They tested it on two boards: One is a "Celoxica RC200" with a Xilinx Virtex II XC2V1000. The other their own "Pilchard" memory interface board with a Xilinx XCV1000E. That board seems to be designed for data processing (mainly cryptograhy, it seems).
But they claim a extreme good SNR (up to 170db at low playing levels; but 115db seem more likely for realistic scenarios).
Due to the rather dodgy quality of the paper, and since I could not find a follow-up paper (seems they did that for a conference), I suppose that was the work of a student who decided he could build a DAC for home use and his final thesis
As I said, dodgy
As I understood Noah, he is using "only" a third order SDM, and the graphs in the paper look a lot as if they achieve their... uhm... good results with a fifth order SDM. So the noise shaping becomes steeper, and [I'd guess] requires a steeper filter between the the FPGA and the audio sink.
They also interpolate data points, so effectively they are are over-sampling at 96kHz*64 = 6.144MHz. No idea how big that impact is.
Noah: I read some stuff on FPGAs and am very impressed with what you're doing! The TE board seems quite nice feature wise, but the whole Zinq platform seems to be not exactly beginners turf. If you're getting somewhere with that, I *really* have to disciple myself from ordering one; especially considering word at this years LLVM conference was that they're interested in compiling for FPGAs
Yeah, I have the advantage that FPGA tech has come a long way since the Virtex II. Five generations, actually, I'm using an Artix/Zynq 7.
They upsampled up to 192x, I'm actually using ~2000x upsampling of a 48KHz signal. I've looked into higher order sigma-delta, but you end up needing to restrict the amplitude and throw away linearity as you do so. (e.g., quantizing at double the max amplitude puts you one bit farther away from where the SDM works best, and so on.)
That much upsampling eases the restrictions on the analog-side output filter considerably too. No need for high-order cutoffs and such.
A quick simulation shows that their claim of >140dB SNR is easily achievable for sine waves no more than ~3 bits below peak... Which isn't really representative in my opinion, almost all of the troubles I've run into are when the music quiets down.
That 3-bit figure is without interpolation, though. The FPGA can easily pull FIR filters with thousands of taps to do interpolation, but I've not ironed out all the details.
@ArchmidesMP Not only is the Zynq platform not "beginners turf", that TE board is a royal pain above and beyond the usual Zynq difficulties. It *is* cheap, though. Even after you throw in the cost of a JTAG adapter.
Also... what's an apodizing filter?
They upsampled up to 192x, I'm actually using ~2000x upsampling of a 48KHz signal. I've looked into higher order sigma-delta, but you end up needing to restrict the amplitude and throw away linearity as you do so. (e.g., quantizing at double the max amplitude puts you one bit farther away from where the SDM works best, and so on.)
That much upsampling eases the restrictions on the analog-side output filter considerably too. No need for high-order cutoffs and such.
A quick simulation shows that their claim of >140dB SNR is easily achievable for sine waves no more than ~3 bits below peak... Which isn't really representative in my opinion, almost all of the troubles I've run into are when the music quiets down.
That 3-bit figure is without interpolation, though. The FPGA can easily pull FIR filters with thousands of taps to do interpolation, but I've not ironed out all the details.
@ArchmidesMP Not only is the Zynq platform not "beginners turf", that TE board is a royal pain above and beyond the usual Zynq difficulties. It *is* cheap, though. Even after you throw in the cost of a JTAG adapter.
Also... what's an apodizing filter?
Some people worry about the post-ringing and especially the pre-ringing of all the steep FIR filters you normally find in a digital audio signal chain. Peter Craven came up with a trick to reduce the pre- and post-ringing and called it an apodizing filter.
The idea is to put one filter somewhere in the record-playback chain that has a stopband that starts just before the transition bands of all the other filters. This special filter must have controlled ringing, that is, it must have a relatively smooth roll-off and possibly a non-linear phase response in its transition and stop bands to reduce pre-ringing at the expense of some extra post-ringing.
The whole thing only makes sense when you believe signals in the transition bands of the steep filters to be audible, at least when heard in combination with the rest of the signal. If you can't hear anything above 20 kHz under any circumstances, filters whose transition bands start at or above 20 kHz are in fact already apodized by your ears.
In any case, it's an interesting idea and it is easy to incorporate on an FPGA.
I don't understand your comment about high-order sigma-deltas. As far as I know, you already have to worry about stability at large input signals and about recovery from overload when you use a third-order sigma-delta, so why do you use third rather than second order?
The idea is to put one filter somewhere in the record-playback chain that has a stopband that starts just before the transition bands of all the other filters. This special filter must have controlled ringing, that is, it must have a relatively smooth roll-off and possibly a non-linear phase response in its transition and stop bands to reduce pre-ringing at the expense of some extra post-ringing.
The whole thing only makes sense when you believe signals in the transition bands of the steep filters to be audible, at least when heard in combination with the rest of the signal. If you can't hear anything above 20 kHz under any circumstances, filters whose transition bands start at or above 20 kHz are in fact already apodized by your ears.
In any case, it's an interesting idea and it is easy to incorporate on an FPGA.
I don't understand your comment about high-order sigma-deltas. As far as I know, you already have to worry about stability at large input signals and about recovery from overload when you use a third-order sigma-delta, so why do you use third rather than second order?
I've actually found that second order works best for that reason, I just mentioned third in the first post because it's where I started. I think I got a 5th order working once too... not sure.
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