S/PDIF and PLL

[anubis260]

So after some rest, and new ideas I'm far in the project. I made the whole part of the S/PDIF decoder. I totally rejected the internal clock and PLL. The triggering of the whole scheme lies on the restored clock from input signal. Which is probably going to say "output jitter = source jitter" Is that good?

 

[DF96]

If you run SPDIF with no PLL then you get 'output jitter = source jitter + cable jitter'. The PLL gets rid of the cable jitter, and any HF components of the source jitter. This means that it will have worse jitter than a traditional SPDIF setup.