Look at the web signature for more
The question on mixer is: Does Andera use miniComponents mixer's?
While mixing the source should be sine alike and will try with some SMD 7 * 5 using 16.368 & 16.369 farnel gear.
I go far deeper with up to 33Mio FFT as 1.4milli Herz Bin width to get the beef. But shows the limitations of the used clock oscillators.
I need a 24.576 or an 2 * 12.288 solution with ultimate low PN.
May same issues about the used xco on RTX and having a accurate sine source as fs/4 or 10kHz to validate
While measure jitter with a 10G/s DSO, you will get 100ps sample intervals, so no deal to measure with a histogram a 1 ps jitter
Hp
"The question on mixer is: Does Andera use miniComponents mixer's"
It's on the board - MCL ASK-1...
But I'm afraid that it would be complicated to 'abuse' that doubler board. All connections are fixed, the whole thing is very specialized.
What regards RTX, Jens had put NDK SD clocks in it, as far as I know.
It's on the board - MCL ASK-1...
But I'm afraid that it would be complicated to 'abuse' that doubler board. All connections are fixed, the whole thing is very specialized.
What regards RTX, Jens had put NDK SD clocks in it, as far as I know.
First of all, it is not just one transition that the polynomial fit is executed on.. Then, we are talking 20/30k€ / k$ machines and above. A lot of pain was put in that adc precision, linearity, and sampling jitter.
Also true, though, that properly the use of GHz sampling rate guarantees a very high close-in phase noise floor.
So definitely these are not good tools to use for looking at these applications we are talking about here.
But perfectly usable above say, the kHz zone. And the jitter analysis packets will say a world more about problem sources (like we have seen with deterministic jitter). And there are so much fine differentiations even inside the deterministic jitter family..
So I continue not to understand the 'looking down' attitude toward these things.
Would also add, that getting used to these algorithms can give some intuitive experience in how to tune the performance, trick the procedure, sharpen the view finder..
Reassuming: not good tools for low noise oscillator design. Invaluable tools for system clock debugging, (also audio..), communications links debugging etc.
Ciao, George
Also true, though, that properly the use of GHz sampling rate guarantees a very high close-in phase noise floor.
So definitely these are not good tools to use for looking at these applications we are talking about here.
But perfectly usable above say, the kHz zone. And the jitter analysis packets will say a world more about problem sources (like we have seen with deterministic jitter). And there are so much fine differentiations even inside the deterministic jitter family..
So I continue not to understand the 'looking down' attitude toward these things.
Would also add, that getting used to these algorithms can give some intuitive experience in how to tune the performance, trick the procedure, sharpen the view finder..
Reassuming: not good tools for low noise oscillator design. Invaluable tools for system clock debugging, (also audio..), communications links debugging etc.
Ciao, George
In the meantime, I am trying my best to get a working phase noise setup. This is a result with which I am quite happy, it proved to be more difficult than I had thought of..
It's a direct measurement of a Crystek CCHD950, 80MHz XO as implemented in a Buffalo II board.
The setup is the Holme analyser. I am using a 148MHz Valpey Fisher oscillator az ADC clock, that turned out to be fundamental.
Actually I like these Crystek products, one can use them as yardstick in searching for a reference performance..
It's a direct measurement of a Crystek CCHD950, 80MHz XO as implemented in a Buffalo II board.
The setup is the Holme analyser. I am using a 148MHz Valpey Fisher oscillator az ADC clock, that turned out to be fundamental.
Actually I like these Crystek products, one can use them as yardstick in searching for a reference performance..
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Yes, I am a happy HPW-Works user..
Thank you ! Sorry HpW, must have been half asleep when reading Joseph K's post
what is this scale -1 to 5? is it the power of 10 in (Hz) ? so 0,1Hz to 10kHz ?
Just for fun, take the new Driscoll or Differential oscillators at 22 MHz and add a couple of frequency doublers, then add 6dB for each duplication.
The phase noise at 10 Hz from the carrier will be around -118dBc for 90 MHz output, only 50dB better than the Crystek at 80 MHz.
Moreover, since the duplication does not add phase noise very close to the carrier one could expect -67dBC at 0.1 Hz from the carrier, like the base 22MHz oscillator.
Maybe the Crystek is not just the best oscillator to drive the Buffalo.
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From the above plot we can see that in the real world the frequency duplication adds less than 3 db (-135.8 to -133), then we can expect even -124dBc at 10 Hz from the carrier for a 90 MHz oscillator, so almost 60 dB better than the Crystek.
Maybe the Buffalo could sounds better, I hope someone try it and report the impressions.
Maybe the Buffalo could sounds better, I hope someone try it and report the impressions.
Did you build the phase noise measurement instrument to measure the noise floor?
If so I believe it was better if you saved 1000 Euro.
Or else you could use this money to buy a Lecroy real time digital oscilloscope since you trust more the oscilloscope than a phase noise measurement system ("Without a picosecond time of hesitation.
The instrument which is telling me the truth.
In this specific case, the oscilloscope.").
When something seems to be too good to be true, it usually is.
That begins with the alleged 3 dB per duplication, the real world cannot
be unphysical.
Nobody can rightfully expect -124 dBc / 10Hz / 90MHz.
Even Pascall is 20 dB worse, and the _entry_ level subtypes
did cost quite a few K€ when I asked their German distributor
some years ago.
And the Holmes design is in the very same league as the timepod,
main difference is the missing integration into timelab.
A good starting point with a Spartan-6 eval board and a quad LT ADC.
cheers, Gerhard.
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Thanks Joseph, good work
and sorry I made thing more confusing by typing 10kHz in stead of 100kHz (of course I know what 10 to the power of 5 means
I have just seen you own LP12/EKOS/KANDID, the best choice!
Is this Klaus' audio system?
I was in Koeln in 2019 May and I met Klaus and Hans to listen to Klaus' system.
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Gerhard,
I agree with you in principle but the above phase noise plot (11 to 22 MHz) shows clearly 3dB worse at 10 Hz and almost no difference at 1 Hz and 0.1 Hz from the carrier.
This is the real world by real measurements, the 1/F3 phase noise is not affected by the frequency doubler, the 1/f noise is around 3 dB worse, while the noise floor increases by 6 dB or just a little more.
I'm not surprised because the 1/f3 is driven by the crystal (random walk of the crystal), so IMHO the physics is confirmed.
Anyway as soon as we have built the down converter we will measure the real phase noise of the duplicated 90 MHz.
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