The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator

[andrea_mori]

Yes, 1kV DC is scary.

[diyiggy]

well can be more with a 845

[andrea_mori]

Preview of the whole Lite system under testing.

[G600]

A beast coming!

[lindamar]

Exciting news Andrea !!

With regards to the I2S receiver, it seems to be HDMI right ?

I am definitely in for the DAC and the FIFO

[andrea_mori]

Yes, the I2S receiver is over HDMI, it's the TWSAFB-RX.
The transmitter is the TWSAFB-TX.

[BPatrik]

Andrea. Do you think that HDMI interface for I2S is optimal?

[laserscrape]

HDMI is before the fifo+isolator, it shouldn't make any difference.

[andrea_mori]

Originally Posted by BPatrik

Andrea. Do you think that HDMI interface for I2S is optimal?

I think the source is not much important, the FIFO should isolate the DAC from the source since they work in different time domains.

[andrea_mori]

Originally Posted by laserscrape

HDMI is before the fifo+isolator, it shouldn't make any difference.

Yes, the jitter coming from the source cannot affect the DAC because the FIFO isolates them.
Data incoming from the source are stored in a memory and then they coming out with a different master clock, the FIFO is asynchronous.

The quality of the output depends on the quality of the FIFO master clock.