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-   -   Signalyst DSC1 (https://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1.html)

Signalyst 2nd November 2014 09:00 PM

Quote:

Originally Posted by mcluxun (https://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1-post4109178.html#post4109178)
Do I need 3.3v on other pins: 7, 10 and 11.

Just on the pin 10, pin 9 is the other 3V3 pin, but it is not connected. Note the non-standard pin numbering on the Amanero connector! So pin 10 is the top-left pin (you can see trace on the solder side goes to C1).

Quote:

And for SCJ1 I should short 1 and 2?
Yes... This makes the DSDEN signal control latch-enable on the 595. So when there is no DSD data, output latches are in high-impedance state.

LeonBernieniv 4th November 2014 02:20 AM

mcluxun, sorry for my memory about R1, I never set it to 1K when I check it just now.
The gain was by value=432r of R806, Sounds really great but loudness still not enough.
When I try to chang R1 to 1K from 500r, distortion can be heard.15K/32=468.75r, 8K/32=250r you know. So set the gain on output stage is the right way.

Signalyst 4th November 2014 07:45 AM

I didn't get any notable increase in distortion by setting R1 to 1K. 2nd harmonic in the output is around -80 dB and higher order harmonics at lower levels. Increased level at the intermediate stages increases distortion a little since it is relative to level, but also increases SNR.

Reason why I changed my mind for this is that at 0-point half of the latches are on, thus 15K/16=937.5 and 8K/16=500. So on average, the source is half of the total resistance.

You can of course also change gain by placing suitable resistor at R806/R816 which are there, but marked "NI" (Not Installed) for that reason.

LeonBernieniv 4th November 2014 10:11 AM

Sorry for my word expression. The source impedance is 468.75r on full range and the source current is 10.67mA p-p, mapped to R1 should be 10.67V p-p if R1 is 1K, gain=-2.13. Sounds seems been clipping distortion. Perhaps this is 'a case' on my side.

mcluxun 5th November 2014 03:50 AM

To make it easier I ve actually shorted the relay.

Right now I'm still getting very loud noise. Any hint where should I start looking?

Signalyst 10th November 2014 10:48 PM

Quote:

Originally Posted by LeonBernieniv (https://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1-post4110830.html#post4110830)
Sorry for my word expression. The source impedance is 468.75r on full range and the source current is 10.67mA p-p, mapped to R1 should be 10.67V p-p if R1 is 1K, gain=-2.13. Sounds seems been clipping distortion. Perhaps this is 'a case' on my side.

It shouldn't ever have more than about 75% of the elements in same state, otherwise the input signal is illegal...

Signalyst 10th November 2014 11:01 PM

Quote:

Originally Posted by mcluxun (https://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1-post4111857.html#post4111857)
To make it easier I ve actually shorted the relay.

Right now I'm still getting very loud noise. Any hint where should I start looking?

It would be good to verify the wiring if you are not using Amanero input board...

Of course supply voltages for all chips, check that the enable line at shift registers is stable so that the latches stay enabled. Scope or logic analyzer on bit clock and data lines at the shift register end. If you have spectrum analyzer, then checking out the output at resistor network.

This design should be pretty simple to debug even with just plain scope, since there's just one clock and two data lines...

mcluxun 27th November 2014 03:41 AM

Quote:

Originally Posted by Signalyst (https://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1-post4118171.html#post4118171)
It would be good to verify the wiring if you are not using Amanero input board...

Of course supply voltages for all chips, check that the enable line at shift registers is stable so that the latches stay enabled. Scope or logic analyzer on bit clock and data lines at the shift register end. If you have spectrum analyzer, then checking out the output at resistor network.

This design should be pretty simple to debug even with just plain scope, since there's just one clock and two data lines...

So embarrassing.... it's a grounding issue.
here's the 1k sine wave
https://i.imgur.com/Jtsy1gn.jpg

LeonBernieniv 27th November 2014 06:44 AM

1 Attachment(s)
Good tool! I am very interested to see what will happen after this:

Signalyst 27th November 2014 09:13 PM

Quote:

Originally Posted by LeonBernieniv (https://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1-post4134938.html#post4134938)
Good tool! I am very interested to see what will happen after this:

In this picture there is still missing PSU feed for IC1/IC2 that is normally coming from the Amanero +3.3V output...

I tried to make a clarifying picture:
An externally hosted image should be here but it no longer works. Please upload images instead of linking to them to prevent this.


(the DSC1 PSU board has suitable 3.3V output for the purpose)


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