Audio master clock distribution for a modular DSP board design

[apvw]

Hi all,

I am currently designing a modular DSP board with up to 8 channels of ADC and DAC and/or digital audio outputs. The design consists of a main board with 12 expansion slots. Each slot can either hold a ADC/AES input board or DAC/AES output board. Or it can be left empty.

My headache is caused by the design of the 24.576MHz master clock distibution network and keeping the jitter as low as possible.

My first idea was to use a main PECL or LVDS or similair distribution line and use stubs to each expansion board. I have 3 concerns however which may impair the signal quality:
1) Trace length: What distances can I make using a PECL/LVDS
2) What is the influence of the card connector: I have not yet selected a suitable connector, but will probably be some kind of fine-pitch header
3) What is the influence of the stubs: How long can they be and what happens when no card is placed and the stubs are thus left open.

My second idea is to use 50ohm coaxial cables with MCX or similair connectors. Here i have also some concerns:
1) Which are suitable drivers to drive the 50 ohm coax and do not add significant jitter. I have tried searching this forum, but haven't been able to find any solutions.
2) What is a suitable to be used as fanout buffer? As there are 12 expansion slots and a DSP, I need 13 outputs. I am also thinking of bringing one clock to the outside for future interfacing/synchronizing of external devices.
3) As a possible solution to avoid the need of that many parallel outputs, daisy chaining might be an option. However, how do I implement this as I am not able to find any tee adapters for those small coaxial cables. And what will it do to the quality of the signal?

I hope that someone here can give me some suggestions or ideas

Thanks!

Alex

 

[twest820]

Sims and a look through the various clock group's product portfolios and design collateral should answer most of the above. Some searching will fill in a decent chunk of the rest. Without more specificity it's difficult to say much meaningful about the tradeoffs between additive jitter in lower cost implementations and those which employ jitter cleaners as they apply to what you're designing.

25MHz is slow enough lumped parameter extraction from a field solver on the connectors is probably fine. It's probable parameter sweeps at the lower cost end of things would show board to board impedance matching as the dominant issue. But it'll depend on many factors not specified above. You may want to do some monte carlo to characterize the solution space.

 

[apvw]

Sims and a look through the various clock group's product portfolios and design collateral should answer most of the above. Some searching will fill in a decent chunk of the rest. Without more specificity it's difficult to say much meaningful about the tradeoffs between additive jitter in lower cost implementations and those which employ jitter cleaners as they apply to what you're designing.

Believe me, I have been searching the Internet for about 2 weeks now. The comment about the hadache is not a lie. The manufacturers of clock fanout buffers etc. give information, but they are not very specific about additive jitter. The jitter is mostly specified for > 10 kHz bands. Secondly, when I would use a fanout buffer, I'd need up to 14 outputs. There aren't many fanout buffers available for that, and most of them use an internal PLL which you cannot bypass. The fanout buffer must have outputs which can be individually disabled also for when a card is not placed. So this means putting several smaller fanout buffers in series and parallel, which causes more jitter and also skew as a bonus. And the use of jitter cleaners is something I want to avoid. This shouldn't be necessary for a system with a well designed clock distribution network.

To avoid stacking up fanout buffers I explored the possibilitie of using a LVDS or similar transmission line in a multidrop configuration. An LVDS to single-ended receiver is then placed on each expansion card. However, I haven't been able to find any real specification of the effect on the signal integrity and thus jitter in relation to the number of drops you make and the length of the line. Also much depends on the PCB layout, with which I am not very experienced. I guess I am able to lay out a 100 or so ohm differential line and I know I should avoid using vias, but I have never actually done this and seen the result on a scope or something. That's one of the reasons I posted this thread. To find out the experiences others have had with this kind of solution.

The other possible solution I came up with is the use of 50 or 75 ohm coaxial cables for the distribution. This would solve the PCB layout and connector issues. However, I am having trouble finding a suitable driver. I have seen people using a few logic buffers in parallel. But this would not give me the voltage levels at the end of the line to directly drive the clock input of the parts that require the clock. So some sort of level translation would be needed here.
A possible solution for increasing the drive level that was suggested on another forum, is to use a high speed (video) op-amp. But how can I jugde which op-amp is suitable? What is the performance of such an op-amp regarding to additive jitter?

Regarding the lack of specificity: I am not sure which additional info you would need. But I'll give it a shot.
The system will consist of a 'motherboard' with a DSP and MCU. This motherboard will have 12 card slots that can hold an ADC/DAC or SPDIF in- output card. I hope be able to limit the number of layers for all PCBs to 4.
All of the parts I use on the expansion cards require a single ended 3V3 low jitter clock (the ADC/DAC boards at least). Some of them need 24.576MHz and some 12.288MHz. Those who need 12.288MHz will perform the /2 division locally. So a 24.576MHz master clock is all that's required by each card.
The idea of using expansion cards is that I can grow the system as I need. Firstly I want to use it in a 2 channel setup. This is mainly because of budgetary reasons, but I also want to make sure the design is what I expect from it before investing any more. As my wallet allows it, I can expand the system up to a 8 channel setup for driving 8 amplifiers. Also this design allows a very flexible setup regarding bi-amping or dual subwoofers, experimenting with several types of DAC and ADC or even expand the system with other functionality.

25MHz is slow enough lumped parameter extraction from a field solver on the connectors is probably fine. It's probable parameter sweeps at the lower cost end of things would show board to board impedance matching as the dominant issue. But it'll depend on many factors not specified above. You may want to do some monte carlo to characterize the solution space.

I am sorry, but you lost me here. Parameter extraction? Field solver? Parameter sweep. Board to board impedance? Monte Carlo? Solution space? Could you please explain this a bit for the 'dummie' that I am?

 

[twest820]

Hmm, I guess I'd suggest two things. One is to build your signal integrity skills to where you can simulate a line with a few stubs and assess the ISI. Once you have that sweeping parameter variations for layout options, termination selection, component tolerances, and PCB assembly variations is somewhat tedious but straightforward. The other is to define a phase noise requirement, since without one there's no formal way to reason about whether a design is good enough or not. As you've noted, some amount of estimation is likely to be required close in.

 

[jcx]

on the other hand you could read the actual psychoacoustic controlled, DBT listening test evidence for jitter audibility thresholds - not the calcs of S/N floor effect or Sighted, "I clearly heard the improvement, even my wife in the kitchen..." typical anecdotes that pass for evidence among audiophiles

then you can concentrate on merely competent engineering rather than OCD over picosecond levels