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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 14th August 2012, 12:44 AM   #851
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by Rosendorfer View Post
Hi Regal

Not that I disagree this is of cause true, but as far as I know, the same could be told about connection from Spidf to FIFO as this as well will be:"corrected by the reclock" and there Ian is using u.FL.
Well more..... there are u.FL sockets ready waiting at output of FIFO board that when connecting FIFI to Clock Board, just cannot be used because of lack of u.FL inputs at Clock board input.

Rosendorfer
Hi Rosendorfer,

The u.fl sockets for I2S output on the FIFO board are for those who need connecting I2S signals direct from FIFO board without passing through re-clock logic on the clock board.

With the re-clock function from the clock board, the output jitte will be determined by the MCLK but I2S signals which need to be re-clocked (they are synchronized with MCLK). That why I didn't include u.fl sockets for clock board input.

Actually there are two sync pipline stages in the FIFO KIT, one is inside FPGA, the other is on the clock board. The only thing is that the power supply on the FIFO board is not as good as PSU on the clock board.

Regards,

Ian
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Old 14th August 2012, 11:42 AM   #852
Rosendorfer is offline Rosendorfer  Poland
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Hi Ian

It was just my small R&D curiosity question, and now my curiosity is fully satisfied .
Even if still at that one connection I will not be able to use that very professional looking u.FL cables....

If I may have a wish .... that one day You could add USB input to Your Spidf board and make it kind of "Ultimate Digital Input Board"......
Having seen quality of Your designs and dedication to details, bet that would have been killer product.

Rosendorfer
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Old 14th August 2012, 08:38 PM   #853
ENSen is offline ENSen  Sweden
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
I will connect the FIFO and 3 ttl level SPDIF to my B-III. Would it cause any problems to connect also the SPDIF inputs via u.fl. I know they are 50 ohm and not 75 ohm which should be used for SPDIF but the alternative is to solder them to the B-III adapter board which will not be 75 ohm either.
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Old 15th August 2012, 03:27 AM   #854
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by Rosendorfer View Post
Hi Ian

It was just my small R&D curiosity question, and now my curiosity is fully satisfied .
Even if still at that one connection I will not be able to use that very professional looking u.FL cables....

If I may have a wish .... that one day You could add USB input to Your Spidf board and make it kind of "Ultimate Digital Input Board"......
Having seen quality of Your designs and dedication to details, bet that would have been killer product.

Rosendorfer
Thanks Rosendorfer, Will take consideration.

Ian
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Old 15th August 2012, 03:39 AM   #855
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Originally Posted by ENSen View Post
I will connect the FIFO and 3 ttl level SPDIF to my B-III. Would it cause any problems to connect also the SPDIF inputs via u.fl. I know they are 50 ohm and not 75 ohm which should be used for SPDIF but the alternative is to solder them to the B-III adapter board which will not be 75 ohm either.
All spdif signals to BIII are converted to LVTTL level. They are no longer original 75ohm S/PDIF coaxial signals. So don't worry about the 75 ohm issue.

I didn't see any problem connecting LVTTL spdif signal to BIII with a 50 ohm u.fl cable. That impedance is close to the impendance of a PCB trace, and, it would be perfect if the signal has 50 ohm impendance matching at source.

Ian
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Old 15th August 2012, 05:09 AM   #856
ENSen is offline ENSen  Sweden
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by iancanada View Post
All spdif signals to BIII are converted to LVTTL level. They are no longer original 75ohm S/PDIF coaxial signals. So don't worry about the 75 ohm issue.

I didn't see any problem connecting LVTTL spdif signal to BIII with a 50 ohm u.fl cable. That impedance is close to the impendance of a PCB trace, and, it would be perfect if the signal has 50 ohm impendance matching at source.

Ian
Ok, thanks Ian.
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Old 17th August 2012, 03:54 PM   #857
Rosendorfer is offline Rosendorfer  Poland
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Hi Ian

Last night I was pooking around FiFo board with my scope and found something for small R&D question.
Seems that rise and fall times for BitClock at FiFo output is about 5ns and after reclocking by ultra fast FlipFlop's rise and fall times at ClockBoard output goes UP to about 10ns...!?
I could expect rather opposite ..
Not that it can influence SQ in any way but just find it bit puzzling.

Rosendorfer
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File Type: jpg Bit_Clk_Fifo_out_rise_fall.jpg (309.8 KB, 518 views)
File Type: jpg Bit_Clk_Fifo_out_fall_5ns.jpg (291.6 KB, 510 views)
File Type: jpg Ian_ClockBoard_out_probe.jpg (410.6 KB, 495 views)
File Type: jpg Bit_Clk_ClockBoard_out_rise_fall.jpg (286.0 KB, 493 views)
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Old 18th August 2012, 02:35 AM   #858
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by Rosendorfer View Post
Hi Ian

Last night I was pooking around FiFo board with my scope and found something for small R&D question.
Seems that rise and fall times for BitClock at FiFo output is about 5ns and after reclocking by ultra fast FlipFlop's rise and fall times at ClockBoard output goes UP to about 10ns...!?
I could expect rather opposite ..
Not that it can influence SQ in any way but just find it bit puzzling.

Rosendorfer
Hi Rosendorfer,

You did very interesting test.

Actually, without the serial resistor, the tr and tf are mainly decided by the output dynamic current. While, with that source impedance matching resistor, the tr and tf will be mainly decided by the capacitive of the load. tr and rf are not constant, they have big relationship with the circuit parameters.

The PicoGate FF on the clock board is rated at 550 MHz with testing condition at 3.3V Vcc and 5pf CL and without Rs. So the worst case tr and tf should be better than 2.2ns. However, if you increased CL to 30Pf, the worst case tr and tf will become 5ns. But to measure tr and tf accurately at ns level, oscilloscope with mare than 1GHz bandwidth is required.

Different from the PicoGate FF, each output port of the FPGA has an internal driver, so the output current will be higher than a flip-flop. However, the high dynamic current will result in high EMI noise on the ground floor, that’s why I have to include a secondary re-clock flip-flop with independent low noise PSU on the clock board. The rated peak-peak jitter of an output of FPGA could go up to 300ps, but the output phase noise of a flip-flop will be roughly only 6dB worth than the MCLK. You might be already noticed the difference on the waveform noise from your testing result even the 50MHz bandwidth still not big enough.

You can try to output I2S signals directly from FIFO board to see if there is any sonic difference. A DS DAC usually does not sensitive to the I2S jitter (will sensitive to MCLK jitter), but a NOS DAC does.

Thank you for sharing you experience.

Have a nice weekend.

Ian

Last edited by iancanada; 18th August 2012 at 02:37 AM.
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Old 18th August 2012, 07:24 AM   #859
pinnocchio is offline pinnocchio  Canada
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anyone knows at which thread hookup MCLK from FIFO to BII is discussed. This is using the u.fl cables. I will be using the FIFO + dual clock board.

Thanks
Do
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Old 18th August 2012, 01:10 PM   #860
rdowdall is offline rdowdall  United States
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Hello Ian - Do you have documentation I2S FIFO project that I could look at?. I am currently building a BIII

Thanks,

Rick
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